參數(shù)資料
型號： EVAL-ADUC7036QSPZ
廠商： Analog Devices Inc
文件頁數(shù)： 52/132頁
文件大?。?/td> 0K
描述： BOARD EVAL FOR ADUC7036
設計資源： EVAL-ADUC7036 Schematic & Brd Outline
EVAL ADUC7036 Gerber Files
標準包裝： 1
系列： QuickStart™ PLUS 套件
主要目的： 電源管理，電池監(jiān)控器
嵌入式： 是，MCU，16/32 位
已用 IC / 零件： ADuC7036
已供物品： 板，線纜，文檔，仿真器，電源，軟件
ADuC7036
Rev. C | Page 26 of 132
The FEE0CON and FEE1CON Registers section to the FEE0MOD and FEE1MOD Registers section provide detailed descriptions of the
bit designations for each of the Flash/EE control MMRs.
FEE0CON and FEE1CON Registers
Name: FEE0CON and FEE1CON
Address: 0xFFFF0E08 and 0xFFFF0E88
Default Value: 0x07
Access: Read/write access
Function: These 8-bit registers are written by user code to control the operating modes of the Flash/EE memory controllers for Block 0
(32 kB) and Block 1 (64 kB).
Table 13. Command Codes in FEE0CON and FEE1CON
Code
Command
Reserved
Reserved. This command should not be written by user code.
Single read
Load FEExDAT with the 16-bit data indexed by FEExADR.
Single write
Write FEExDAT at the address pointed by FEExADR. This operation takes 50 μs.
Erase write
Erase the page indexed by FEExADR and write FEExDAT at the location pointed by FEExADR. This operation takes 20 ms.
Single verify
Compare the contents of the location pointed by FEExADR to the data in FEExDAT. The result of the comparison is
returned in FEExSTA, Bit 1 or Bit 0.
Single erase
Erase the page indexed by FEExADR.
Mass erase
Erase Block 0 (32 kB) or Block 1 (64 kB) of user space. The 2 kB kernel is protected. This operation takes 1.2 sec. To
prevent accidental execution, a command sequence is required to execute this instruction (see the Command
0x07
Default command.
0x08
Reserved
Reserved. This command should not be written by user code.
0x09
Reserved
Reserved. This command should not be written by user code.
0x0A
Reserved
Reserved. This command should not be written by user code.
0x0B
Signature
FEE0CON: This command results in the generation of a 24-bit linear feedback shift register (LFSR)-based signature
that is loaded into FEE0SIG.
If FEE0ADR is less than 0x97800, this command results in a 24-bit LFSR-based signature of the user code space from
the page specified in FEE0ADR upwards, including the kernel, security bits, and Flash/EE key.
If FEE0ADR is greater than 0x97800, the kernel and manufacturing data are signed. This operation takes 120 μs.
FEE1CON: This command results in the generation of a 24-bit LFSR-based signature, beginning at FEE1ADR and
ending at the end of the 63,500 block, that is loaded into FEE1SIG. The last page of this block is not included in the
sign generation.
0x0C
Protect
This command can be run only once. The value of FEExPRO is saved and can be removed only with a mass erase
(0x06) or with the software protection key.
0x0D
Reserved
Reserved. This command should not be written by user code.
0x0E
Reserved
Reserved. This command should not be written by user code.
0x0F
Ping
No operation, interrupt generated.
1 The x represents 0 or 1, designating Flash/EE Block 0 or Block 1.
2 The FEE0CON register reads 0x07 immediately after the execution of this command.
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