參數(shù)資料
型號： EVAL-ADUC7036QSPZ
廠商： Analog Devices Inc
文件頁數(shù)： 6/132頁
文件大?。?/td> 0K
描述： BOARD EVAL FOR ADUC7036
設計資源： EVAL-ADUC7036 Schematic & Brd Outline
EVAL ADUC7036 Gerber Files
標準包裝： 1
系列： QuickStart™ PLUS 套件
主要目的： 電源管理，電池監(jiān)控器
嵌入式： 是，MCU，16/32 位
已用 IC / 零件： ADuC7036
已供物品： 板，線纜，文檔，仿真器，電源，軟件
ADuC7036
Rev. C | Page 103 of 132
HANDLING INTERRUPTS FROM THE HIGH
VOLTAGE PERIPHERAL CONTROL INTERFACE
An interrupt controller is integrated with the high voltage circuits.
If the interrupt controller is enabled through IRQEN[16], one of
six high voltage sources can assert the high voltage interrupt
(IRQ3) signal and interrupt the MCU core.
Although the normal MCU response to this interrupt event is
to vector to the IRQ or FIQ vector address, the high voltage
interrupt controller simultaneously and automatically loads the
current value of the high voltage status register (HVSTA) into the
HVDAT register. During this time, the busy bit in HVCON[0] is
set to indicate that a transfer is in progress and then is cleared
after 10 μs to indicate the HVSTA contents are available in HVDAT.
The interrupt handler, therefore, can poll the busy bit in HVCON
until it deasserts. After the busy bit is cleared, HVCON[1] must
be checked to ensure that the data was read correctly. Next, the
HVDAT register can be read. At this time, HVDAT holds the value
of the HVSTA register. The status flags can then be interrogated
to determine the exact source of the high voltage interrupt, and
the appropriate action can be taken.
LOW VOLTAGE FLAG (LVF)
The ADuC7036 features a low voltage flag (LVF) that allows the
user to monitor REG_DVDD. When enabled via HVCFG0[2],
the low voltage flag can be monitored through HVMON[3]. If
REG_DVDD drops below 2.1 V, HVMON[3] is cleared and the
RAM contents are corrupted. After the low voltage flag is enabled,
it is reset only by REG_DVDD dropping below 2.1 V or by
disabling the LVF functionality using HVCFG0[2].
HIGH VOLTAGE DIAGNOSTICS
It is possible to diagnosis fault conditions on the WU, LIN, and
STI pins, as described in Table 78.
Table 78. High Voltage Diagnostics
High
Voltage Pin
Fault Condition
Method
Result
Short between LIN or
STI and VBAT
Drive LIN or STI low
LIN or STI short-circuit interrupt is generated after 20 μs if
more than 100 mA is continuously drawn.
LIN or STI
Short between LIN or
STI and GND
Drive LIN or STI high
LIN or STI readback reads back low.
Short between wake-up
and VBAT
Drive WU low
Readback high in HVMON[7].
Short between wake-up
and GND
Drive WU high
WU short-circuit interrupt is generated after 400 μs if more
than 100 mA typically is sourced.
WU
Open circuit
Enable OC diagnostic resistor
with WU disabled
HVMON[7] is cleared if the load is connected and set if WU is
open-circuited.
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