參數資料
型號： EVAL-ADUC7036QSPZ
廠商： Analog Devices Inc
文件頁數： 54/132頁
文件大?。?/td> 0K
描述： BOARD EVAL FOR ADUC7036
設計資源： EVAL-ADUC7036 Schematic & Brd Outline
EVAL ADUC7036 Gerber Files
標準包裝： 1
系列： QuickStart™ PLUS 套件
主要目的： 電源管理，電池監(jiān)控器
嵌入式： 是，MCU，16/32 位
已用 IC / 零件： ADuC7036
已供物品： 板，線纜，文檔，仿真器，電源，軟件
ADuC7036
Rev. C | Page 28 of 132
FEE0DAT and FEE1DAT Registers
Name: FEE0DAT and FEE1DAT
Address: 0xFFFF0E0C and 0xFFFF0E8C
Default Value: 0x0000
Access: Read/write access
Function: This 16-bit register contains the data either read from
or to be written to the Flash/EE memory.
FEE0MOD and FEE1MOD Registers
Name: FEE0MOD and FEE1MOD
Address: 0xFFFF0E04 and 0xFFFF0E84
Default Value: 0x00
Access: Read/write access
Function: These registers are written by user code to configure
the mode of operation of the Flash/EE memory controllers.
Table 15. FEE0MOD and FEE1MOD MMR Bit Designations
Bit
Description1
15 to 7
Not used. These bits are reserved for future functionality and should be written as 0 by user code.
6, 5
Flash/EE security lock bits. These bits must be written as [6:5] = 10 to complete the Flash/EE security protect sequence.
4
Flash/EE controller command complete interrupt enable.
Set to 1 by user code to enable the Flash/EE controller to generate an interrupt upon completion of a Flash/EE command.
Cleared to disable the generation of a Flash/EE interrupt upon completion of a Flash/EE command.
3
Flash/EE erase/write enable.
Set by user code to enable the Flash/EE erase and write access via FEExCON.
Cleared by user code to disable the Flash/EE erase and write access via FEExCON.
2
Reserved. Should be written as 0.
1
Flash/EE controller abort enable.
Set to 1 by user code to enable the Flash/EE controller abort functionality.
0
Reserved. Should be written as 0.
1 The x represents 0 or 1, designating Flash/EE Block 0 or Flash/EE Block 1.
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