
MOTOROLA
4-10
INSTRUCTION SET
CPU32
REFERENCE MANUAL
ory. The bit number is specified as immediate data or in a data register. Register op-
erands are 32 bits long, and memory operands are 8 bits long.
Table 4-6
is a summary
of bit manipulation instructions.
4.3.7 Binary-Coded Decimal (BCD) Instructions
Five instructions support operations on BCD numbers. The arithmetic operations on
packed BCD numbers are add decimal with extend (ABCD), subtract decimal with ex-
tend (SBCD), and negate decimal with extend (NBCD).
Table 4-7
is a summary of the
BCD operations.
4.3.8 Program Control Instructions
A set of subroutine call and return instructions and conditional and unconditional
branch instructions perform program control operations.
Table 4-8
summarizes these
instructions.
Table 4-6 Bit Manipulation Operations
Instruction
Syntax
Dn,
ea
#
data
,
ea
Dn,
ea
#
data
,
ea
Dn,
ea
#
data
,
ea
Dn,
ea
#
data
,
ea
Operand Size
8, 32
8, 32
8, 32
8, 32
8, 32
8, 32
8, 32
8, 32
Operation
BCHG
(
bit number
of destination)
→
Z
→
bit of destination
BCLR
(
bit number
of destination)
→
Z;
0
→
bit of destination
(
bit number
of destination)
→
Z;
1
→
bit of destination
(
bit number
of destination)
→
Z
BSET
BTST
Table 4-7 Binary-Coded Decimal Operations
Instruction
Syntax
Dn, Dn
– (An), – (An)
Operand Size
8
8
8
8
8
8
Operation
ABCD
Source
10
+ Destination
10
+ X
→
Destination
NBCD
ea
0 – Destination
10
– X
→
Destination
SBCD
Dn, Dn
– (An), – (An)
Destination
10
– Source
10
– X
→
Destination
Table 4-8 Program Control Operations
Instruction
Syntax
Operand Size
Conditional
8, 16, 32
16
Operation
Bcc
DBcc
label
Dn
,
label
If condition true, then PC + d
→
PC
If condition false, then Dn – 1
→
PC;
if Dn
≠ (
–
1), then PC + d
→
PC
If condition true, then destination bits are set to one;
else, destination bits are cleared to zero
Unconditional
8, 16, 32
PC + d
→
PC
8, 16, 32
SP – 4
→
SP; PC
→
(SP); PC + d
→
PC
Scc
ea
8
BRA
BSR
label
label
F
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n
.