
CPU32
REFERENCE MANUAL
OVERVIEW
MOTOROLA
1-1
SECTION 1 OVERVIEW
The CPU32, the first-generation instruction processing module of the M68300 Family,
is based on the industry-standard MC68000 processor. It has many features of the
MC68010 and MC68020, as well as unique features suited for high-performance con-
troller applications. The CPU32 is source code and binary code compatible with the
M68000 Family.
CPU32 power consumption during normal operation is low because it is a high-speed
complementary metal-oxide semiconductor (HCMOS) device. Power consumption
can be reduced to a minimum during periods of inactivity by executing the low-power
stop (LPSTOP) instruction, which shuts down the CPU32 and other intermodule bus
(IMB) submodules.
Ease of programming is an important consideration in using a microcontroller. The
CPU32 instruction format reflects a predominately register-memory interaction philos-
ophy. All data resources are available to all operations requiring those resources.
There are eight multifunction data registers and seven general-purpose addressing
registers. The data registers readily support 8-bit (byte), 16-bit (word), and 32-bit (long
word) operand lengths for all operations. Address manipulation is supported by word
and long-word operations. Although the program counter (PC) and stack pointers (SP)
are special purpose registers, they are also available for most data addressing activi-
ties. Ease of program checking and diagnosis is enhanced by trace and trap capabil-
ities at the instruction level.
As controller applications become more complex and control programs become larger,
high-level language (HLL) will become the system designer's choice in programming
languages. HLL aids rapid development of complex algorithms, with less error, and is
readily portable. The CPU32 instruction set will efficiently support HLL.
1.1 Features
Features of the CPU32 are as follows:
Fully Upward Object Code Compatible with M68000 Family
Virtual Memory Implementation
Loop Mode of Instruction Execution
Fast Multiply, Divide, and Shift Instructions
Fast Bus Interface with Dynamic Bus Port Sizing
Improved Exception Handling for Controller Applications
Enhanced Addressing Modes
— Scaled Index
— Address Register Indirect with Base Displacement and
— Expanded PC Relative Modes
— 32-Bit Branch Displacements
Instruction Set Enhancements
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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