
CPU32
REFERENCE MANUAL
MOTOROLA
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SECTION 1 OVERVIEW
1.1
1.1.1
1.1.2
1.1.3
1.1.4
1.1.5
1.1.6
1.1.6.1
1.1.6.2
1.1.7
1.1.8
1.2
Features ....................................................................................................1-1
Virtual Memory ..................................................................................1-2
Loop Mode Instruction Execution ......................................................1-2
Vector Base Register ........................................................................1-3
Exception Handling ...........................................................................1-3
Enhanced Addressing Modes ...........................................................1-4
Instruction Set ...................................................................................1-4
Table Lookup and Interpolation Instructions .............................1-4
Low-Power Stop Instruction ......................................................1-6
Processing States .............................................................................1-6
Privilege States .................................................................................1-6
Block Diagram ...........................................................................................1-6
SECTION 2ARCHITECTURE SUMMARY
2.1
2.2
2.3
2.3.1
2.3.1.1
2.3.1.2
2.3.1.3
2.3.2
Programming Model ..................................................................................2-1
Registers ...................................................................................................2-2
Data Types ................................................................................................2-3
Organization in Registers ..................................................................2-4
Data Registers ..........................................................................2-4
Address Registers .....................................................................2-5
Control Registers ......................................................................2-5
Organization in Memory ....................................................................2-6
SECTION 3 DATA ORGANIZATION AND ADDRESSING CAPABILITIES
3.1
3.2
3.3
3.4
3.4.1
3.4.1.1
3.4.1.2
3.4.2
3.4.2.1
3.4.2.2
3.4.2.3
3.4.2.4
3.4.2.5
3.4.2.6
Program and Data References ..................................................................3-1
Notation Conventions ................................................................................3-2
Implicit Reference ......................................................................................3-2
Effective Address ......................................................................................3-3
Register Direct Mode .........................................................................3-3
Data Register Direct ..................................................................3-3
Address Register Direct ............................................................3-3
Memory Addressing Modes ...............................................................3-4
Address Register Indirect ..........................................................3-4
Address Register Indirect With Postincrement ..........................3-4
Address Register Indirect With Predecrement ..........................3-4
Address Register Indirect With Displacement ...........................3-5
Address Register Indirect With Index (8-Bit Displacement) ......3-5
Address Register Indirect With Index (Base Displacement) .....3-6
TABLE OF CONTENTS
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