
CPU32
REFERENCE MANUAL
INSTRUCTION EXECUTION TIMING
MOTOROLA
8-7
In the following equations, negative tail values are used to negate the effects of a slow-
er bus. The equations are generalized, however, so that they may be used on any
speed bus with any tail value.
NEW_TAIL
=
OLD_TAIL
+
(NEW_CLOCK – 2)
IF ((NEW_CLOCK – 4) >0) THEN
NEW_CYCLE = OLD_CYCLE
+
(NEW_CLOCK -2)
+
(NEW_CLOCK – 4)
ELSE
NEW_CYCLE = OLD_CYCLE
+
(NEW _CLOCK – 2)
where:
NEW_TAIL/NEW_CYCLE is the adjusted tail/cycle at the slower speed
OLD_TAIL/OLD_CYCLE is the value listed in the instruction timing tables
NEW_CLOCK is the number of clocks per cycle at the slower speed
Note that many instructions listed as having negative tails are change of flow instruc-
tions, and that the bus speed used in the calculation is that of the new instruction
stream.
8.2 Instruction Stream Timing Examples
The following programming examples provide a detailed examination of timing effects.
In all examples, memory access is either from internal two-clock memory or from ex-
ternal synchronous memory, the bus is idle, and the instruction pipeline is full at start.
8.2.1 Timing Example 1: Execution Overlap
Figure 8-4 illustrates execution overlap caused by the bus controller's completion of
bus cycles while the sequencer is calculating the next effective address. One clock is
saved between instructions, as that is the minimum time of the individual head and tail
numbers.
Instructions
MOVE.WA1, (A0)
+
ADDQ.W#1, (A0)
CLR.W$30 (A1)
Figure 8-4 Example 1 — Instruction Stream
WRITE
FOR 1
1 PRE-
FETCH
READ
FOR 2
WRITE
FOR 2
2 PRE-
FETCH
ADDQ
TO <EA>
ADDQ.W #1,(AO)
EA FETCH
ADDQ
MOVE A1,(AO)+
MOVE.W A1,(AO)+
EA CALC
CLR
CLR
<EA>
3 PRE-
FETCH
3 PRE-
FETCH
WRITE
FOR 3
CLR.W $30(A1)
CLOCK
1
2
3
4
5
6
7
8
9
0
1
2
3
4
5
6
7
8
BUS
CONTROLLER
INSTRUCTION
CONTROLLER
EXECUTION
TIME
F
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n
.