
MOTOROLA
3-6
DATA ORGANIZATION AND ADDRESSING CAPABILITIES
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CPU32
REFERENCE MANUAL
“Ri” specifies a general data or address register used as an index register. The index
operand is derived from the index register. The index register is a data register if bit
[15] = 0 in the first extension word and an address register if bit [15] = 1. The index
register number is given by extension word bits [14:12].
Index size is referred to as “sz”. It may be either “W” or “L”. Index size is given by bit
[11] of the extension word. If bit [11] = 0, the index value is the sign-extended low-order
word integer of the index register (W). If bit [11] = 1, the index value is the long integer
in the index register (L).
The term “scl” refers to index scale selection and may be 1, 2, 4, or 8. The index value
is scaled according to bits [10:9]. Codes 00, 01, 10, or 11 select index scaling of 1, 2,
4, or 8, respectively.
3.4.2.6 Address Register Indirect With Index (Base Displacement)
The full format indexed addressing mode requires an index register indicator and an
optional 16- or 32-bit sign-extended base displacement. The index register indicator
includes size and scale information. In this mode, the operand is in memory. The ad-
dress of the operand is the sum of the contents of the address register, the scaled con-
tents of the sign-extended index register, and the base displacement.
+
+
OPERAND
0
31
0
31
0
31
X
MEMORY ADDRESS
INTEGER
SIGN EXTENDED
SIGN-EXTENDED VALUE
SCALE VALUE
0
7
GENERATION:
ASSEMBLER SYNTAX:
MODE:
REGISTER:
ADDRESS REGISTER:
DISPLACEMENT:
INDEX REGISTER:
SCALE:
MEMORY ADDRESS:
NUMBER OF EXTENSION WORDS: 1
31
EA = (An) + (Xn*SCALE) + d
(d8
,
110
n
An
8
SIGN-EXTENDED VALUE
+
+
OPERAND
0
31
0
31
0
31
X
MEMORY ADDRESS
SIGN-EXTENDED VALUE
SCALE VALUE
0
GENERATION:
ASSEMBLER SYNTAX:
MODE:
REGISTER:
ADDRESS REGISTER:
INDEX REGISTER:
SCALE:
MEMORY ADDRESS:
NUMBER OF EXTENSION WORDS: 1, 2, OR 3
31
n
An
110
EA = (An) + (Xn*SCALE) + bd
(bd, An, Xn. SIZE*SCALE)
BASE DISPLACEMENT:
F
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n
.