
CPU32
REFERENCE MANUAL
INSTRUCTION EXECUTION TIMING
MOTOROLA
8-21
8.3.12 Control Instructions
The control instruction table indicates the number of clock periods needed for the pro-
cessor to perform the specified operation on the given addressing mode. Footnotes
indicate when to account for the appropriate effective address times. The total number
of clock cycles is outside the parentheses. The numbers inside parentheses (r/p/w)
are included in the total clock cycle number. All timing data assumes two-clock reads
and writes.
NOTE: The CHK2 instruction involves a save step which other instructions do not have. To
calculate total the instruction time, calculate the Save, the effective address, and
the Operation execution times, and combine in the order listed, using the equations
given in
8.1.6 Instruction Execution Time Calculation
.
8.3.13 Exception-Related Instructions and Operations
The exception-related instructions and operations table indicates the number of clock
periods needed for the processor to perform the specified exception-related actions.
No additional tables are needed to calculate total effective execution time for these in-
structions. The total number of clock cycles is outside the parentheses. The numbers
inside parentheses (r/p/w) are included in the total clock cycle number. All timing data
assumes two-clock reads and writes.
Instruction
Head
0
0
0
2
2
2
3
3
1
2
2
1
2
1
2
0
3
0
2
0
0
0
1
1
1
1
Tail
2
2
2
0
0
0
2
2
2
0
2
1
0
1
2
2
2
0
0
0
0
0
2
2
2
0
Cycles
12(0/2/0)
12(0/2/0)
12(0/2/0)
6(0/2/0)
6(0/2/0)
6(0/2/0)
13(0/2/2)
13(0/2/2)
13(0/2/2)
8(0/1/0)
42(2/2/6)
3(0/1/0)
18(X/0/0)
3(0/1/0)
52(x
+
2/1/6)
6(0/2/0)
13(0/2/2)
2(0/1/0)
10(0/2/2)
10(0/3/2)
2(0/1/0)
8(0/1/2)
12(2/2/0)
14(3/2/0)
12(2/2/0)
9(2/1/0)
ANDI
EORI
ORI
ANDI
EORI
ORI
BSR.B
BSR.W
BSR.L
CHK
CHK
CHK2 (Save)
CHK2 (Op)
CHK2 (Save)
CHK2 (Op)
JMP
JSR
LEA
LINK.W
LINK.L
NOP
PEA
RTD
RTR
RTS
UNLK
X = There is one bus cycle for byte and word operands and two bus cycles for long operands.
For long bus cycles, add two clocks to the tail and to the number of cycles.
#, SR
#, SR
#, SR
#, CCR
#, CCR
#, CCR
FEA
, Dn (no ex)
FEA
, Dn (ex)
FEA
, Dn (no ex)
FEA
, Dn (no ex)
FEA
, Dn (ex)
FEA
, Dn (ex)
CEA
CEA
CEA
, An
An, #
An, #
CEA
#
An
F
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n
.