
CPU32
REFERENCE MANUAL
INSTRUCTION EXECUTION TIMING
MOTOROLA
8-1
SECTION 8 INSTRUCTION EXECUTION TIMING
This section describes the instruction execution timing of the CPU32. External clock
cycles are used to provide accurate execution and operation timing guidelines, but not
exact timing for every possible circumstance. This approach is used because exact
execution time for an instruction or operation depends on concurrency of independent-
ly scheduled resources, on memory speeds, and on other variables.
An assembly language programmer or compiler writer can use the information in this
section to predict the performance of the CPU32. Additionally, timing for exception
processing is included so that designers of multitasking or real-time systems can pre-
dict task-switch overhead, maximum interrupt latency, and similar timing parameters.
Instruction timing is given in clock cycles to eliminate clock frequency dependency.
8.1 Resource Scheduling
The CPU32 contains several independently scheduled resources. The organization of
these resources within the CPU32 is shown in
Figure 8–1
. Some variation in instruc-
tion execution timing results from concurrent resource utilization. Because resource
scheduling is not directly related to instruction boundaries, it is impossible to make an
accurate prediction of the time required to complete an instruction without knowing the
entire context within which the instruction is executing.
8.1.1 Microsequencer
The microsequencer either executes microinstructions or awaits completion of ac-
cesses necessary to continue microcode execution. The microsequencer supervises
the bus controller, instruction execution, and internal processor operations such as
calculation of effective address and setting of condition codes. It also initiates instruc-
tion word prefetches after a change of flow and controls validation of instruction words
in the instruction pipeline.
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