
MOTOROLA
8-18
INSTRUCTION EXECUTION TIMING
CPU32
REFERENCE MANUAL
8.3.7 Binary-Coded Decimal and Extended Instructions
The binary-coded decimal and extended instruction table indicates the number of
clock periods needed for the processor to perform the specified operation using the
specified addressing mode. No additional tables are needed to calculate total effective
execution time for these instructions. The total number of clock cycles is outside the
parentheses. The numbers inside parentheses (r/p/w) are included in the total clock
cycle number. All timing data assumes two-clock reads and writes.
8.3.8 Single Operand Instructions
The single operand instruction table indicates the number of clock periods needed for
the processor to perform the specified operation using the specified addressing mode.
The total number of clock cycles is outside the parentheses. The numbers inside pa-
rentheses (r/p/w) are included in the total clock cycle number. All timing data assumes
two-clock reads and writes.
Instruction
Head
2
2
2
2
0
2
0
2
1
Tail
0
2
0
2
0
2
0
2
0
Cycles
4(0/1/0)
12(2/1/1)
4(0/1/0)
12(2/1/1)
2(0/1/0)
10(2/1/1)
2(0/1/0)
10(2/1/1)
8(2/1/0)
ABCD
ABCD
SBCD
SBCD
ADDX
ADDX
SUBX
SUBX
CMPM
Dn, Dm
(An),
(Am)
Dn, Dm
(An),
(Am)
Dn, Dm
(An),
(Am)
Dn, Dm
(An),
(Am)
(An)+, (Am)+
Instruction
Head
0
0
0
0
0
0
0
0
0
2
0
2
2
4
1
0
Tail
0
2
0
3
0
3
0
3
0
0
2
0
2
0
0
0
Cycles
2(0/1/0)
4(0/1/x)
2(0/1/0)
5(0/1/x)
2(0/1/0)
5(0/1/x)
2(0/1/0)
5(0/1/x)
2(0/1/0)
4(0/1/0)
6(0/1/1)
4(0/1/0)
6(0/1/1)
6(0/1/0)
10(0/1/1)
2(0/1/0)
CLR
CLR
NEG
NEG
NEGX
NEGX
NOT
NOT
EXT
NBCD
NBCD
Scc
Scc
TAS
TAS
TST
X = There is one bus cycle for byte and word operands and two bus cycles for long
operands. For long bus cycles, add two clocks to the tail and to the number of
cycles.
Dn
CEA
Dn
FEA
Dn
FEA
Dn
FEA
Dn
Dn
FEA
Dn
CEA
Dn
CEA
FEA
F
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