參數(shù)資料
型號(hào)： CDB8952
廠商： Cirrus Logic, Inc.
英文描述： CrystalLAN 100BASE-X and 10BASE-T Transceiver
中文描述： CrystalLAN個(gè)100Base - X和10Base - T的收發(fā)器
文件頁(yè)數(shù)： 69/82頁(yè)
文件大?。?/td> 1130K
代理商： CDB8952
CS8952
CrystalLAN
100BASE-X and 10BASE-T Transceiver
69
MII Interface Pins
COL/PHYAD0 - Collision Detect/PHY Address 0. Input/Tri-State Output, Pin 48.
Asserted active-high to indicate a collision on the medium during half-duplex operation. In full-duplex
operation, COL is undefined and should be ignored. When configured for 10 Mb/s operation, COL is
also used to indicate a Signal Quality Error (SQE) condition.
At power-up or at reset, the logic value on this pin is latched into bit 0 of the PHY Address field of the
Self Status Register (address 19h). This pin includes a weak internal pull-up (> 150 K
), or the value
may be set by an external 4.7 K
pull-up or pull-down resistor.
CRS/PHYAD2 - Carrier Sense/PHY Address 2. Input/Tri-State Output, Pin 49.
The operation of CRS is controlled by the REPEATER pin as follows:
At power-up or at reset, the logic value of this pin is latched into bit 2 of the PHY Address Field of the
Self Status Register (address 19h). This pin includes a weak internal pull-down (> 20 K
), or the value
may be set by an external 4.7 K
pull-up or pull-down resistor.
MDC - Management Data Clock. Input, Pin 28.
Input clock used to transfer serial data on MDIO. The maximum clock rate is 16.67 MHz. This clock may
be asynchronous to RX_CLK and TX_CLK.
MDIO - Management Data Input/Output. Bi-Directional, Pin 27.
Bi-directional signal used to transfer management data between the CS8952 and the Ethernet controller.
In order to conform with Annex 22B of the IEEE 802.3u specification, the MII_DRV pin should be pulled
high during power-up or reset, and the MDIO pin should have an external 1.5 K
pull-up resistor. For
systems not required to drive external connectors and cables as described in the IEEE802.3u
specification, the external pull-up resistor may not be necessary.
MII_IRQ - MII Interrupt. Open Drain Output, Pin 26.
Asserted low to indicate the status corresponding to one of the unmasked interrupt status bits in the
Interrupt Status Register (address 11h) has changed. It will remain low until the ISR is read, clearing all
status bits.
This open drain pin requires a 4.7 k
pull-up resistor.
RX_CLK - Receive Clock. Tri-State Output, Pin 36
Continuous clock output used as a reference clock for sampling RXD[3:0], RX_ER, and RX_DV.
RX_CLK will have the following nominal frequency:
REPEATER pin
high
low
low
DUPLEX mode
don
’
t care
full duplex
half duplex
CRS Indicates
receive activity only
receive activity only
receive or transmit activity
Speed
100 Mb/s
10 Mb/s
10 Mb/s
10BT_SER pin
n/a
low (parallel)
high (serial)
Nominal frequency
25 MHz
2.5 MHz
10 MHz
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