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參數(shù)資料
| 型號： | CDB8952 |
| 廠商： | Cirrus Logic, Inc. |
| 英文描述： | CrystalLAN 100BASE-X and 10BASE-T Transceiver |
| 中文描述： | CrystalLAN個100Base - X和10Base - T的收發(fā)器 |
| 文件頁數(shù)： | 62/82頁 |
| 文件大小： | 1130K |
| 代理商： | CDB8952 |
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CS8952
62
CrystalLAN
100BASE-X and 10BASE-T Transceiver
6.20
10BASE-T Configuration Register - Address 1Ch
15
14
13
12
11
10
9
8
Reserved
7
6
5
4
3
2
1
0
National
Compatibility
Mode
LED3 Blink
Enable
Enable LT/10
SQE Enable
Reserved
Low Rx
Squelch
Polarity
Disable
Jabber Enable
BIT
15:8
7
NAME
TYPE
RESET
DESCRIPTION
Reserved
National Compati-
bility Mode
Read Only
Read/Write 1
0000 0000
When set, registers and bits that are not compatible
with the National DP83840 are disabled and writes to
these registers are ignored.
When set, LED3 will blink during auto-negotiation
and will indicate Link Good status upon completion of
auto-negotiation. When clear, LED3 indicates Link
Good status only.
6
LED3 Blink Enable
Read/Write 0
Note:
This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit (bit
7) is set.
When set, this bit enables the transmission of link
pulses.
5
Enable LT/10
Read/Write 1
When clear, link pulses are disabled and a good link
condition is forced. If link pulses are disabled during
100 Mb/s operation with auto-negotiation enabled,
the CS8952 will go into 10 Mb/s mode. If operating in
100 Mb/s mode with no auto-negotiation, then clear-
ing this bit has no effect.
When set, and if the CS8952 is in half-duplex mode,
this bit enables the 10BASE-T SQE function. When
the part is in repeater mode, this bit is cleared and
may not be set.
This bit should be read as a don
’
t care and, when
written, should be written to 1.
When clear, the 10BASE-T receiver squelch thresh-
olds are set to levels defined by the ISO/IEC 8802-3
specification. When set, the thresholds are reduced
by approximately 6 dB. This is useful for operating
with
“
quiet
”
cables that are longer than 100 meters.
The 10BASE-T receiver automatically determines
the polarity of the received signal at the RXD+/RXD-
input. When this bit is clear, the polarity is corrected,
if necessary. When set, no effort is made to correct
the polarity. Polarity correction will only be performed
during 10BASE-T packet reception.
4
SQE Enable
Read/Write Reset to the logic
inverse of the
value on the
REPEATER pin.
Read Only
1
3
Reserved
2
Low Rx Squelch
Read/Write 0
1
Polarity Disable
Read/Write 0
Note:
This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit (bit
7) is set.
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