參數(shù)資料
型號(hào): CDB8952
廠商: Cirrus Logic, Inc.
英文描述: CrystalLAN 100BASE-X and 10BASE-T Transceiver
中文描述: CrystalLAN個(gè)100Base - X和10Base - T的收發(fā)器
文件頁數(shù): 54/82頁
文件大?。?/td> 1130K
代理商: CDB8952
CS8952
54
CrystalLAN
100BASE-X and 10BASE-T Transceiver
9
MF Preamble
Enable
Read/Write 0
When set, this bit will force all management frames
(via MDIO, MDC) to be preceded by a 32 bit pream-
ble pattern of contiguous ones to be considered
valid. When cleared, it allows management frames
with or without the preamble pattern. The status of
this register is (inversely) reflected in the MF Pream-
ble bit in the Basic Mode Status Register (address
01h).
Note:
This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
When set, internal timers are sped up significantly in
order to facilitate production test. Leave clear for
proper operation.
8
Fast Test
Read/Write 0
Note:
This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
Setting this bit will disable (tri-state) the CLK25 out-
put pin, reducing digital noise and power consump-
tion.
7
CLK25 Disable
Read/Write When TCM pin is
low, reset to 1;
otherwise, reset to
0
Read/Write 1
6
Enable LT/100
When set, normal link status checking is enabled.
When clear, this bit forces the link status to Link OK
(at 100 Mb/s), and will assert the LINK_OK LED.
When set, this bit forces the Carrier Integrity Monitor
function to be disabled. When low, the Carrier Integ-
rity Monitor function is enabled, and detection of an
unstable link will disable the receive and transmit
functions.
When set, this bit forces the 10 Mb/s and 100 Mb/s
outputs to be inactive. When clear, normal transmis-
sion is enabled.
5
CIM Disable
Read/Write Reset to the logic
inverse of the
value on the
REPEATER pin.
4
Tx Disable
Read/Write 0
If Tx Disable is set while a packet is being transmit-
ted, transmission is completed and no subsequent
packets are transmitted until Tx Disable is cleared
again. Also, if Tx Disable is cleared while TX_EN is
high, the transmitter will remain disabled until TX_EN
is deasserted. This prevents fragments from being
transmitted onto the network.
BIT
NAME
TYPE
RESET
DESCRIPTION
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