參數(shù)資料
型號(hào)： CDB8952
廠商： Cirrus Logic, Inc.
英文描述： CrystalLAN 100BASE-X and 10BASE-T Transceiver
中文描述： CrystalLAN個(gè)100Base - X和10Base - T的收發(fā)器
文件頁(yè)數(shù)： 35/82頁(yè)
文件大?。?/td> 1130K
代理商： CDB8952
CS8952
CrystalLAN
100BASE-X and 10BASE-T Transceiver
35
3
Auto-Neg Ability
Read Only
1
This bit indicates that the CS8952 has auto-negotia-
tion capability. Therefore this bit will always read
back a value of 1.
When set, this bit indicates that a valid link has been
established. Upon a link failure, this bit is cleared and
latched. It will remain cleared until this register is
read.
In 10BASE-T mode, if the last transmission is longer
than 105 ms, then the packet output is terminated by
the jabber logic and this bit is set. If JabberiE (Inter-
rupt Mask Register (address 10h), bit 3) is set, an MII
Interrupt will be generated.
2
Link Status
Read Only
0
1
Jabber Detect
Read Only
0
This bit is implemented with a latching function so
that the occurrence of a jabber condition causes it to
become set until it is cleared by a read to this regis-
ter, a read to the Interrupt Status Register (address
11h), or a reset.
No jabber detect function has been defined for
100BASE-TX.
This bit indicates that an extended register set may
be accessed (registers beyond address 01h). This bit
always reads back a value of 1.
0
Extended Capability Read Only
1
BIT
NAME
TYPE
RESET
DESCRIPTION
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