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參數(shù)資料
| 型號： | CDB8952 |
| 廠商： | Cirrus Logic, Inc. |
| 英文描述： | CrystalLAN 100BASE-X and 10BASE-T Transceiver |
| 中文描述： | CrystalLAN個100Base - X和10Base - T的收發(fā)器 |
| 文件頁數(shù)： | 30/82頁 |
| 文件大?。?/td> | 1130K |
| 代理商： | CDB8952 |
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CS8952
30
CrystalLAN 100BASE-X and 10BASE-T Transceiver
A read transaction is indicated by an Opcode of 10
and a write by 01.
The PHY Address is five bits, with the most signif-
icant bit sent first. If the PHY address included in
the frame is not 00000 or does not match the PHY-
AD field of the Self Status Register (address 19h),
the rest of the frame is ignored.
The register address is five bits, with the most sig-
nificant bit sent first, and indicates the CS8952 reg-
ister to be written to/read from.
The Turnaround time is a two bit time spacing be-
tween when the MAC drives the last register ad-
dress bit onto MDIO and the data field of a
management frame in order to avoid contention
during a read transaction. For a read transaction,
the MAC should tri-state the MDIO pin beginning
on the first bit time, and the CS8952 will begin
driving the MDIO signal to a logic ZERO during
the second bit time. During write transactions,
since the MDIO direction does not need to be re-
versed, the MAC will drive the MDIO to a logic
ONE for the first bit time and a logic ZERO for the
second.
The data field is always 16 bits in length, with the
most significant bit sent first.
5. CONFIGURATION
TheCS8952canbeconfiguredinavarietyofways.
All control and status information can be accessed
via the MII Serial Management Interface. Addi-
tionally, many configuration options can be set at
power-uporresettimesviaindividualcontrollines.
Some configuration capabilities are available at
any time via individual control lines.
5.1
Configuration At Power-up/Reset
Time
At power-up and reset time, the following pins are
5.2
Thefollowing pinsarefordedicatedcontrolsignals
and can be used at any time to configure the
CS8952.
Configuration Via Control Pins
5.3
The CS8952 supports configuration by software
control through the use of 16-bit configuration and
status registers accessed via the MDIO/MDC pins
(MII Management Interface). The first seven regis-
ters are defined by the IEEE 802.3 specification.
Additional registers extend the register set to pro-
vide enhanced monitoring and control capabilities.
Configuration via the MII
6. CS8952 REGISTERS
The CS8952 register set is comprised of the 16-bit
status and control registers described below. A de-
tailed description each register follows.
Pin Name
10BT_SER
AN[1:0]
BP4B5B
BPALIGN
BPSCR
ISODEF
LPSTRT
PHYAD[4:0]
REPEATER
Function
Select 10BASE-T serial mode
Select auto-negotiation mode
Bypass 4B5B coders
Bypass 4B5B coders and scramblers
Bypass scramblers, enter FX mode
Electrically isolate MII after reset
Start in low power mode
Set MII PHY address
Control definition of CRS pin, enable
carrier integrity monitor and SQE func-
tion
Set MII driver strength
Set TX_CLK mode
TXSLEW[1:0] Set 100BASE-TX transmitter output
slew rate
MII_DRV
TCM
Pin Name
LPBK
PWRDN
RESET
Function
Enter loopback mode
Enter power-down mode
Reset
Register Address
0h
1h
Description
Type
Basic Mode Control Register
Basic Mode Status Register
Read/Write
Read-Only
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