參數(shù)資料
型號(hào)： CDB8952
廠商： Cirrus Logic, Inc.
英文描述： CrystalLAN 100BASE-X and 10BASE-T Transceiver
中文描述： CrystalLAN個(gè)100Base - X和10Base - T的收發(fā)器
文件頁(yè)數(shù)： 42/82頁(yè)
文件大?。?/td> 1130K
代理商： CDB8952
CS8952
42
CrystalLAN
100BASE-X and 10BASE-T Transceiver
6.9
Interrupt Mask Register - Address 10h
This register indicates which events will cause an interrupt event on the MII_IRQ pin. Each bit acts as
an enable to the interrupt. Thus, when set, the event will cause the MII_IRQ pin to be asserted. When
clear, the event will not affect the MII_IRQ pin, but the status will still be reported via the Interrupt Sta-
tus Register (address 11h).
15
14
13
12
11
10
9
8
CIM Link
Unstable
Link Status
Change
Descrambler
Lock Change
PrematureEnd
Error
DCR
Rollover
FCCR
Rollover
RECR
Rollover
Remote
Loopback
Fault
7
6
5
4
3
2
1
0
Reset
Complete
Jabber
Detect
Auto-Neg
Complete
Parallel
Detection Fault
Parallel
Fail
Remote
Fault
Page
Received
Reserved
BIT
15
NAME
TYPE
RESET
DESCRIPTION
CIM Link Unstable
Read/Write 0
When set, an interrupt will be generated if an unsta-
ble link condition is detected by the Carrier Integrity
Monitor function.
Note:
This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
When set, an interrupt will be generated each time
the CS8952 detects a change in the link status.
14
Link Status Change Read Write 1
Note:
This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
When set, an interrupt will be generated each time
the 100BASE-TX receive descrambler loses or
regains synchronization with the far-end.
13
Descrambler Lock
Change
Read/Write 0
Note:
This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
When set, an interrupt will be generated when two
consecutive IDLES are detected in a 100BASE-TX
frame without the ESD sequence.
12
Premature End
Error
Read/Write 0
Note:
This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
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