參數(shù)資料
型號: CDB8952
廠商: Cirrus Logic, Inc.
英文描述: CrystalLAN 100BASE-X and 10BASE-T Transceiver
中文描述: CrystalLAN個100Base - X和10Base - T的收發(fā)器
文件頁數(shù): 56/82頁
文件大?。?/td> 1130K
代理商: CDB8952
CS8952
56
CrystalLAN
100BASE-X and 10BASE-T Transceiver
6.17
Loopback, Bypass, and Receiver Error Mask Register - Address 18h
15
14
13
12
11
10
9
8
Bad SSD
Enable
Bypass 4B5B
Bypass
Scrambler
Bypass
Symbol
Alignment
ENDEC
Loopback
FX Drive
Remote
Loopback
PMD
Loopback
7
6
5
4
3
2
1
0
Strip PreambleAlterCRS
Loopback
Transmit
Disable
Code Error
Report Select
PrematureEnd
Error Report
Select
Link Error
Report Enable
Packet Error
Report Enable
Code Error
Report Enable
BIT
15
NAME
TYPE
RESET
DESCRIPTION
Bad SSD Enable
Read/Write 1
When set, this bit enables the reporting of a bad SSD
(False-Carrier event) on the MII. These events will be
reported by setting RX_ER=1, RX_DV=0, and
RXD[3:0]=1110.
If the 4B5B encoders are being bypassed, this event
will be reported by setting RX_DV=0 and
RXD[4:0]=11110. If symbol alignment is bypassed,
the CS8952 does not detect carrier, and thus will not
report bad SSD events.
When set, this bit causes the receive 5B4B decoder
and the transmit 4B5B encoder to be bypassed.
14
Bypass 4B5B
Read/Write Reset to the value
on the BP4B5B
pin.
Read/Write Reset to the value
on the BPSCR
pin.
13
Bypass Scrambler
When set, this bit causes the receive descrambler
and the transmit scrambler blocks to be bypassed,
and the CS8952 accepts NRZI data from an external
100BASE-FX optical module through pins RX_NRZ+
and RX_NRZ-.
When set, this bit causes the following functions to
be bypassed: receiver descrambling, symbol align-
ment and decoding, transmit symbol encoding, and
transmit scrambling.
When set, the 10BASE-T internal Manchester
encoder output is connected to the decoder input.
When clear, the CS8952 is configured for normal
operation.
This bit controls the drive strength of the 100BASE-
FX PECL interface drivers. When clear, the drivers
are optimized for a 50
load. When set, the drivers
are optimized for a 150
load.
When set, data received from the link is looped back
at the MII and sent back out to the link. Received
data will be presented on the MII pins. Transmit data
at the MII will be ignored.
12
Bypass Symbol
Alignment
Read/Write Reset to the value
on the BPALIGN
pin.
11
ENDEC Loopback
Read/Write 0
10
FX Drive
Read/Write 0
9
Remote Loopback
Read/Write 0
Note:
Setting Remote Loopback and PMD Loopback
simultaneously will cause neither loopback mode to
be entered, and should not be done.
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