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參數(shù)資料
| 型號： | CDB8952 |
| 廠商： | Cirrus Logic, Inc. |
| 英文描述： | CrystalLAN 100BASE-X and 10BASE-T Transceiver |
| 中文描述： | CrystalLAN個100Base - X和10Base - T的收發(fā)器 |
| 文件頁數(shù)： | 26/82頁 |
| 文件大小： | 1130K |
| 代理商： | CDB8952 |
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CS8952
26
CrystalLAN 100BASE-X and 10BASE-T Transceiver
Auto-Negotiation encapsulates information within
aburst ofclosely spaced Link Integrity TestPulses,
referred to as a Fast Link Pulse (FLP) Burst. The
FLP Burst consists of a series of Link Integrity
Pulses which form an alternating clock / data se-
quence. Extraction of the data bits from the FLP
Burst yields aLink Code Word which identifies the
capability of the remote device.
In order to support legacy 10 and 100 Mb/s devic-
es, the CS8952 also supports parallel detection. In
parallel detection, the CS8952 monitors activity on
the media to determine the capability of the link
partner even without auto-negotiation having oc-
curred.
3.3
Resetoccursinresponsetosixdifferentconditions:
Reset Operation
1) There is a chip-wide reset whenever the RE-
SET pin is high for at least 200 ns. During a
chip-wide reset, all circuitry and registers in the
CS8952 are reset.
2) When power is applied, the CS8952 maintains
reset until the voltage at the VDD supply pins
reaches approximately 3.6 V. The CS8952
comesout ofresetonceVDDisgreaterthanap-
proximately 3.6 V and the crystal oscillator has
stabilized.
3) There is a chip-wide reset whenever the RE-
SET bit (bit 15 of the Basic Mode Control Reg-
ister (address 00h)) is set.
4) Digital circuitry is reset whenever bit 0 of the
PCS Sub-Layer Configuration Register (ad-
dress 17h) is set. Analog circuitry is unaffected.
5) Analog circuitry is reset and recalibrated when-
ever the CS8952 enters or exits the power-
down state, as requested by pin PWRDN.
6) Analog circuitry is reset and recalibrated when-
ever the CS8952 changes between 10 Mb/s and
100 Mb/s modes.
Afterareset, theCS8952latchesthesignalson var-
ious input pins in order to initialize key registers
and goes through a self configuration. This in-
cludes calibrating on-chip analog circuitry. Time
required for the reset calibration is typically 40 ms.
External circuitry may access registers internal to
the CS8952 during this time. Reset and calibration
complete is indicated when bit 15 of the Basic
Mode Control Register (address 00h) is clear.
3.4
The LEDx, SPD100, and SPD10 output pins pro-
vide status information that can be used to drive
LEDs or can be used as inputs to external control
circuitry. Indication options include: receive activ-
ity, transmit activity, collision, carrier sense, polar-
ity OK, descrambler synchronization status, auto-
negotiation status, speed (10 vs. 100), and duplex
mode.
LED Indicators
4. MEDIA INDEPENDENT INTERFACE
(MII)
The Media Independent Interface (MII) provides a
simple interconnect to an external Media Access
Controller (MAC). This connection may be chip to
chip, motherboard to daughterboard, or a connec-
tion between two assemblies attached by a limited
length ofshielded cableand an appropriate connec-
tor.
The MII interface uses the following pins:
AN1
AN0
Forced/
Auto
Forced
Forced
Forced
Forced
Auto-Neg
Auto-Neg
Auto-Neg
Auto-Neg
Auto-Neg
Table 5.
Speed
(Mb/s)
10
10
100
100
100/10
10
10
100
100
Full/Half
Duplex
Half
Full
Half
Full
Full/Half
Half
Full
Half
Full
Low
High
Floating
Floating
Floating
Low
Low
High
High
Floating
Floating
Low
High
Floating
Low
High
Low
High
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