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參數(shù)資料
| 型號(hào)： | BT848A |
| 英文描述： | Single-Chip Video Capture for PCI |
| 中文描述： | 單芯片的PCI視頻捕捉 |
| 文件頁(yè)數(shù)： | 91/141頁(yè) |
| 文件大?。?/td> | 1149K |
| 代理商： | BT848A |
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Brooktree
81
PC B
OARD
L
AYOUT
C
ONSIDERATIONS
Latch-up Avoidance
L848A_A
Bt848/848A/849A
Single-Chip Video Capture for PCI
Latch-up Avoidance
Latch-up is a failure mechanism inherent to any CMOS device. It is triggered by
static or impulse voltages on any signal input pin exceeding the voltage on the
power pins by more than 0.5 V, or falling below the GND pins by more than 0.5 V.
Latch-up can also occur if the voltage on any power pin exceeds the voltage on any
other power pin by more than 0.5 V.
In some cases, devices with mixed signal interfaces, such as the Bt848, can ap-
pear more sensitive to latch-up. In reality, this is not the case. However, mixed sig-
nal devices tend to interact with peripheral devices such as video monitors or
cameras that are referenced to different ground potentials, or apply voltages to the
device prior to the time that its power system is stable. This interaction sometimes
creates conditions amenable to the onset of latch-up.
To maintain a robust design with the Bt848, the following precautions should be
taken:
Apply power to the device before or at the same time as the interface cir-
cuitry.
Do not apply voltages below GND–0.5 V, or higher than VAA+0.5 V to
any pin on the device. Do not use negative supply op-amps or any other
negative voltage interface circuitry. All logic inputs should be held low
until power to the device has settled to the specified tolerance.
Connect all VDD, VAA and VPOS pins together through a low imped-
ance plane.
Connect all GND, AGND and VNEG pins together through a low imped-
ance plane.
Figure 39. Optional Regulator Circuitry
I
N
S
YSTEM
P
OWER
(+12 V)
VAA,VDD
(+5 V)
O
UT
G
ROUND
GND
S
UGGESTED
PART
NUMBERS
:
R
EGULATOR
T
EXAS
I
NSTRUMENTS
μ
A78 MO5M
S
YSTEM
P
OWER
(+5 V)
D
IODES
MUST
HANDLE
THE
CURRENT
REQUIREMENTS
OF
THE
Bt848
AND
THE
PERIPHERAL
CIRCUITRY
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