
Brooktree
115
C
ONTROL
R
EGISTER
D
EFINITIONS
GPIO and DMA Control
L848A_A
Bt848/848A/849A
Single-Chip Video Capture for PCI
GPIO and DMA Control
Memory Mapped Location 0x10C – (GPIO_DMA_CTL)
Bits
Type
Default
Name
Description
[15]
RW
0
GPINTC
A value of 0 selects the direct non-inv/inv input from GPINTR to go
to the interrupt status register. A value of 1 selects the rising edge
detect of the GPINTI programmed input.
[14]
RW
0
GPINTI
A value of 1 inverts the input from the GPINTR pin immediately
after the input buffer.
[13]
RW
0
GPWEC
A value of 0 enables GPIO inputs to be registered upon the rising
edge of GPWE. A value of 1 enables GPIO inputs to be registered
upon the falling edge of GPWE.
[12:11]
RW
00
GPIOMODE
00
= Normal GPIO port. See the GPIO section for overriding
conditions.
= Synchronous Pixel Interface output mode.
= Synchronous Pixel Interface input mode.
= Reserved.
01
10
11
[10]
RW
0
GPCLKMODE
A value of 1 enables CLKx1 to be output on GPCLK. A value of 0
disables the output and enables GPCLK to supply the internal pixel
clock during SPI-16 input mode, otherwise this pin is assumed to
be inactive.
[9:8]
RW
00
Reserved
This bit should only be written with a logical zero.
[7:6]
RW
00
PLTP23
Planar mode trigger point for FIFO2 and FIFO3.
00
= 4 DWORDs
01
= 8 DWORDs
10
= 16 DWORDs
11
= 32 DWORDs
[5:4]
RW
00
PLTP1
Planar mode trigger point for FIFO1.
00
= 4 DWORDs
01
= 8 DWORDs
10
= 16 DWORDs
11
= 32 DWORDs
[3:2]
RW
00
PKTP
Packed mode FIFO Trigger Point. The number of DWORDs in the
FIFOs in total before the DMA controller begins to burst data onto
the PCI bus.
00
= 4 DWORDs
01
= 8 DWORDs
10
= 16 DWORDs
11
= 32 DWORDs
[1]
RW
0
RISC_ENABLE
A value of 1 enables the DMA controller to process pixel dataflow
instructions beginning at the RISC program start address.
[0]
RW
0
FIFO_ENABLE
A value of 1 enables the data FIFO, while 0 flushes or resets it.