
Brooktree
109
C
ONTROL
R
EGISTER
D
EFINITIONS
Color Control Register
L848A_A
Bt848/848A/849A
Single-Chip Video Capture for PCI
Color Control Register
Memory Mapped Location 0x0D8 – (COLOR_CTL)
A value of 1 enables byte swapping of data entering the FIFO. B3[31:24] swapped with B2[23:16] and B1[15:8]
swapped with B0[7:0].
Bits
Type
Default
Name
Description
[7]
RW
0
EXT_FRMRATE
When the GPIO port is in SPI-16 input mode then this bit supplies
NTSC(0)/PAL(1) which selects the gamma ROM.
[6]
RW
0
COLOR_BARS
A value of 1 enables a color bars pattern at the input of the VDFC
block.
[5]
RW
0
RGB_DED
A value of 0 enables error diffusion for RGB16/RGB15 modes. A
value of 1 disables it.
[4]
RW
0
GAMMA
A value of 0 enables gamma correction removal. The inverse
gamma correction factor of 2.2 or 2.8 is applied and auto-selected
by the respective mode NTSC/PAL. A value of 1 disables gamma
correction removal.
[3]
RW
0
WSWAP_ODD
WordSwap Odd Field. A value of 1 enables word swapping of data
entering the FIFO. W2[31:16] swapped with W0[15:0]
[2]
RW
0
WSWAP_EVEN
WordSwap Even Field. A value of 1 enables word swapping of
data entering the FIFO. W2[31:16] swapped with W0[15:0]
[1]
RW
0
BSWAP_ODD
ByteSwap Odd Field. A value of 1 enables byte swapping of data
entering the FIFO. B3[31:24] swapped with B2[23:16] and B1[15:8]
swapped with B0[7:0]
[0]
RW
0
BSWAP_EVEN
ByteSwap Even Field. A value of 1 enables byte swapping of data
entering the FIFO. B3[31:24] swapped with B2[23:16] and B1[15:8]
swapped with B0[7:0]