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參數(shù)資料
| 型號(hào)： | BT848A |
| 英文描述： | Single-Chip Video Capture for PCI |
| 中文描述： | 單芯片的PCI視頻捕捉 |
| 文件頁(yè)數(shù)： | 83/141頁(yè) |
| 文件大?。?/td> | 1149K |
| 代理商： | BT848A |
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Brooktree
73
E
LECTRICAL
I
NTERFACES
General Purpose I/O Port
L848A_A
Bt848/848A/849A
Single-Chip Video Capture for PCI
CCIR656
This is a 27 MB/s interface in the form of Cb, Y, Cr, Y, Cb, etc. In this sequence, the
word sequence Cb, Y, Cr, refers to co-sited and color-difference samples and the
following word, Y, corresponds to the next luminance sample.
In this interface there are two timing reference codes (SAV and EAV) that occur
at the start and end of active video. These 4-byte codes occur at the outside bound-
aries of the active video. A 720 pixels in the active video line corresponds to 1440
samples. 1448 bytes make up a video data block (one line of video with reference
codes).
The full video line consists of 1716 bytes (in 525 line systems) and 1728 (in 626
line systems). The line is broken into two parts. The first is blanking, which con-
sists of the front porch, hsync, and back porch, 276 (288 in 635 line systems) bytes
from EAV through SAV. The leading edge of hsync occurs 32 (24 in 625 line sys-
tems) bytes after the start of the digital line. The field interval is aligned to this
leading edge of hsync.
See Figure 34 for a diagram on the interface. For a full reference on this stan-
dard please refer to the CCIR (The International Radio Consultive Committee)
standards directly.
Table 14. Pin Definition of GPIO Port When Using Digital Video-In Mode
GPIO
Signal
Description
Pin
Number
[23]
[22]
[21]
[20]
[19]
[18]
[17]
[16]
[9]
[8]
[7:0]
CLKx1
FIELD
VACTIVE
VSYNC
HACTIVE
HSYNC
Composite ACTIVE
Composite SYNC
VSYNC/FIELD
HSYNC
DATA
Output signals for synchronizing to input video.
82
83
84
85
86
87
88
89
98
99
Input signals for synchronizing to input video.
Cb, Yo, Cr, Y, ... Video data input at GPCLK = CLKx2 rate.
110–117
Figure 34. CCIR 656 or ByteStream Interface to Digital Input Port
CCIR 656 or
ByteStream
Video Generator
(ex. Bt829)
Clock
DATA[7:0]
GPCLK
GPIO[7:0]
Bt848A/849A
8
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