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| 型號(hào)： | BT848A |
| 英文描述： | Single-Chip Video Capture for PCI |
| 中文描述： | 單芯片的PCI視頻捕捉 |
| 文件頁(yè)數(shù)： | 122/141頁(yè) |
| 文件大小： | 1149K |
| 代理商： | BT848A |
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Bt848/848A/849A
Single-Chip Video Capture for PCI
Brooktree
112
C
ONTROL
R
EGISTER
D
EFINITIONS
Interrupt Status
L848A_A
Interrupt Status
Memory Mapped Location 0x100 – (INT_STAT)
This register provides status of pending interrupt conditions. To clear the interrupts, read this register, then write the
same data back. A 1 in the write data clears the particular register bit. The interrupt /status bits can be polled at any
time.
Bits
Type
Default
Name
Description
[31:28]
RO
RISCS
Set when RISC status set bits are set in the RISC instruction.
Reset when RISC status reset bits are set. Status only, no inter-
rupt.
[27]
RO
RISC_EN
A value of 0 indicates the DMA controller is currently disabled. Sta-
tus only, no interrupt.
[26]
RO
Reserved
[25]
RO
RACK
Set when I
2
C operation is completed successfully. Otherwise, if the
receiver does not acknowledge, then this bit will be reset when
I2CDONE is set. Status only, no interrupt.
[24]
RO
FIELD
0 = Odd field, 1 = Even field. Status only, no interrupt.
[23:20]
RO
0000
Reserved
[19]
RR
0
SCERR
Set when the DMA EOL sync counter overflows. This is a severe
error which requires the software to restart the field capture pro-
cess. Also set when SYNC codes do not match in the data/instruc-
tion streams.
[18]
RR
0
OCERR
Set when the DMA controller detects a reserved/unused opcode in
the instruction sequence, or reserved/unused sync status in a
SYNC instruction. In general, this includes any detected RISC
instruction error.
[17]
RR
0
PABORT
Set whenever the initiator receives a MASTER or TARGET
ABORT.
[16]
RR
0
RIPERR
Set when a data parity error is detected (Parity Error Response
must be set) while the initiator is reading RISC instructions.
RISC_ENABLE is reset by the target to stop the DMA immediately.
[15]
RR
0
PPERR
Set when a parity error is detected on the PCI bus for any of the
transactions, R/W, address/data phases, initiator/target,
issued/sampled PERR regardless of the Parity Error Response bit.
All parity errors are serious except for data written to display.
[14]
RR
0
FDSR
FIFO Data Stream Resynchronization occurred. The number of
pixels, lines, or modes passing through FIFO does not match RISC
program expectations.
[13]
RR
0
FTRGT
Set when a pixel data FIFO overrun condition results in the master,
terminating the transaction due to excessive target latency.
[12]
RR
0
FBUS
Set when a pixel data FIFO overrun condition is being handled by
dropping as many DWORDs as needed, indicating bus access
latencies are long.
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