參數(shù)資料
型號(hào)： BT848A
英文描述： Single-Chip Video Capture for PCI
中文描述： 單芯片的PCI視頻捕捉
文件頁數(shù)： 82/141頁
文件大?。?/td> 1149K
代理商： BT848A
Bt848/848A/849A
Single-Chip Video Capture for PCI
Brooktree
72
E
LECTRICAL
I
NTERFACES
General Purpose I/O Port
L848A_A
Digital Video in Support
(Bt848A/849A Only)
This section describes how to use the Bt848A/849A with a digital camera. The
GPIO port can be configured to accept general digital data streams.
The Bt848A/849A contains an SRAM based state machine that isolates the dig-
ital video input events from the internal decoder timing. It allows the digital video
input H & V events to synchronize the sequencer and the programmable output
events to be positioned where needed to synchronize the decoder.
A 20 x 20 SRAM is used to store H & V count values and signal values for gen-
eration of timing events. The SRAM is programmed once for interfacing to a given
digital video input standard. The address for the SRAM is a 20-bit shift register
with reset and advance inputs. The SRAM is written in sequence, in byte-mode, af-
ter a reset. Then the SRAM will function normally in video mode. The addr s/r will
be advanced every time the H or V value compares exactly to the HC or VC
counters, or reset when the HRST signal output is active and the HC reaches the fi-
nal H value. These register settings can be found in the Control Register Digital
Video In Support (Bt848A/849A only).
The digital input port on the Bt848A and Bt849A provides flexibility for inter-
facing to video standards. Software for programming the Bt848A/Bt849A is in-
cluded in the development kit for interfacing to the following standards. Table 14
provides the alternate pin definitions when using the digital video-in mode.
Figure 33. Basic Timing Relationships for SPI Mode
Y[7:0]
C
R
C
B
[7:0]
DVALID
ACTIVE
GPCLK
C
B
FLAG
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