參數(shù)資料
型號(hào): BT848A
英文描述: Single-Chip Video Capture for PCI
中文描述: 單芯片的PCI視頻捕捉
文件頁數(shù): 124/141頁
文件大小: 1149K
代理商: BT848A
Bt848/848A/849A
Single-Chip Video Capture for PCI
Brooktree
114
C
ONTROL
R
EGISTER
D
EFINITIONS
Interrupt Mask
L848A_A
Interrupt Mask
Memory Mapped Location 0x104 – (INT_MASK)
RISC Program Counter
Memory Mapped Location 0x120 – (RISC_COUNT)
RISC Program Start Address
Memory Mapped Location 0x114 – (RISC_STRT_ADD)
Bits
Type
Default
Name
Description
[22:0]
RW
0x000000
A value of 1 enables the interrupt bit. The bits correspond to the
same bits in the Interrupt Status register. Unmasking a bit may
generate an interrupt immediately due to a previously pending
condition. The PCI INTA is level sensitive. It remains asserted until
the device driver clears or masks the pending request.
[23]
RW
0
ETBF
0 =
1 = Enable TritonI PCI controller compatibility.
Normal operation
Bits
Type
Default
Name
Description
[31:0]
RO
RISC_PC
The current value of the RISC program counter. This may be
slightly ahead of the current instruction due to pre-fetching instruc-
tions into the queue.
Bits
Type
Default
Name
Description
[31:0]
RW
0x00000000
RISC_IPC
Base address for the RISC program. Standard 32-bit memory
space byte address, although the software must DWORD align by
setting the lowest two bits to 00. The DMA controller begins exe-
cuting pixel instructions at this address when RISC_ENABLE is
set, i.e. the RISC program counter is loaded with this pointer at the
rising edge of RISC_ENABLE.
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