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| 型號(hào)： | BT848A |
| 英文描述： | Single-Chip Video Capture for PCI |
| 中文描述： | 單芯片的PCI視頻捕捉 |
| 文件頁(yè)數(shù)： | 130/141頁(yè) |
| 文件大?。?/td> | 1149K |
| 代理商： | BT848A |
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Bt848/848A/849A
Single-Chip Video Capture for PCI
Brooktree
120
C
ONTROL
R
EGISTER
D
IGITAL
V
IDEO
I
N
S
UPPORT
(B
T
848A/849A O
NLY
)
Timing Generator Load Byte
L848A_A
Timing Generator Load Byte
Memory Mapped Location 0x080 – (TGLB)
Upon reset, it is initialized to 00.
Timing Generator Control
Memory Mapped Location 0x084 – (TGCTRL)
Upon reset, it is initialized to 00.
Bits
Type
Default
Name
Description
[7:0]
RW
00
TGLB
Load SRAM 1 byte at a time, in sequence after a TGC_AR. Load
the least significant byte first. Each write to this address causes an
automatic advance of the SRAM byte location.
Reading from this address only reads the current byte. The
TGC_AI bit must be pulsed by s/w in order for the SRAM byte loca-
tion to advance.
Bits
Type
Default
Name
Description
0
RW
00
TGC_VM
Timing Generator Video Mode enable.
0
= Read/write mode
1
= Enable timing generator/read mode
1
RW
GPC_AR
Timing Generator Address Reset.
2
RW
TGC_AI
Timing Generator Read Address Increment -active hi pulse incre-
ments the read address.
[4:3]
RW
TGCKI
Decoder Input Clock Select.
00
= Normal xtal 0/xtal 1 mode
01
= PLL
10
= GPCLK
(1)
11
= GPCLK - inverted
(1)
[6:5]
RW
TGCKO
GPCLK Output Clock Select
00
= CLKx1
01
= xtal 0 input
10
= PLL
11
= PLL - inverted
7
–
Reserved
Must be written with a logical zero.
Notes: (1). Since the entire decoder will be running off the external clock GPCLK, when selecting the GPCLK is activat-
ed, the decoder functionality is subject to a halt condition if the input port is disconnected. A clock detect circuit
will allow the decoder to fall back on either the PLL or the Xtal, whichever is enabled via PLL_I. If the PLL has
been put to sleep, then the decoder will fall back on the Xtal0 input. The VPRES status condition indicates the
status of the clock detect output when in digital video input mode which is monitoring GPCLK.
Note that it is desirable for SW to set up the PLL to run at the same frequency as the GPCLK input, so if the
digital camera is disconnected, then blue-field timing will run properly.
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