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參數(shù)資料
| 型號： | BT848A |
| 英文描述： | Single-Chip Video Capture for PCI |
| 中文描述： | 單芯片的PCI視頻捕捉 |
| 文件頁數(shù)： | 21/141頁 |
| 文件大?。?/td> | 1149K |
| 代理商： | BT848A |
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Brooktree
11
F
UNCTIONAL
D
ESCRIPTION
Pin Descriptions
L848A_A
Bt848/848A/849A
Single-Chip Video Capture for PCI
104
NUMXTAL
I
Crystal Format Pin. This pin is set to indicate whether one or
two crystals are present so that the Bt848 can select XT1 or
XT0 as the default in auto format mode. A logical zero on this
pin indicates one crystal is present. A logical one indicates
two crystals are present. This pin is internally pulled up to
VDDG.
JTAG (5 pins)
3
TCK
I
Test clock. Used to synchronize all JTAG test structures.
When JTAG operations are not being performed, this pin
must be driven to a logical low.
5
TMS
I
Test Mode Select. JTAG input pin whose transitions drive the
JTAG state machine through its sequences. When JTAG
operations are not being performed, this pin must be left float-
ing or tied high.
7
TDI
I
Test Data Input. JTAG pin used for loading instructions to the
TAP controller or for loading test vector data for bound-
ary-scan operation. When JTAG operations are not being
performed, this pin must be left floating or tied high.
6
TDO
O
Test Data Output. JTAG pin used for verifying test results of
all JTAG sampling operations. This output pin is active for
certain JTAG operations and will be three-stated at all other
times.
2
TRST
I
Test Reset. JTAG pin used to initialize the JTAG controller.
This pin is tied low for normal device operation. When pulled
high, the JTAG controller is ready for device testing.
Note:Not all PCs drive the PCI bus TRST pin. In these
computers, if the TRST pin on the Bt848 board is connected
to TRST on the PCI bus (which is not driven) the Bt848 may
power up in an undefined state. In these designs, the TRST
pin on the Bt848 card must be tied low (disabling JTAG).
Power & Ground (57 pins)
1, 18, 40,
63, 81,
101, 120
VDD +5V
P
Power supply for digital circuitry. All VDD pins must be con-
nected together as close to the device as possible. A 0.1
μ
F
capacitor should be connected between each group of VDD
pins and the ground plane as close to the device as possible.
130, 134,
136, 148,
152, 156
VAA +5V
VPOS +5V
P
Power supply for analog circuitry. All VAA pins and VPOS
must be connected together as close to the device as possi-
ble. A 0.1
μ
F ceramic capacitor should be connected
between each group of VAA pins and the ground plane as
close to the device as possible.
10, 25,
33, 47,
56, 70, 76
VDDP
PCI VIO
P
Power supply for PCI bus signals. A 0.1
μ
F ceramic capacitor
should be connected between the VDDP pins and the ground
plane as close to the device as possible.
Table 2. Pin Descriptions Grouped by Pin Function
(5 of 6)
Pin #
Pin Name
I/O
Signal
Description
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