
Brooktree
107
C
ONTROL
R
EGISTER
D
EFINITIONS
Video Timing Control
L848A_A
Bt848/848A/849A
Single-Chip Video Capture for PCI
Video Timing Control
Memory Mapped Location 0x6C – Even Field (E_VTC)
Memory Mapped Location 0xEC – Odd Field (O_VTC)
Upon reset, it is initialized to 0x00. VFILT(0) is the least significant bit.
Bits
Type
Default
Name
Description
[7]
RW
0
HSFMT
This bit selects between a single-pixel-wide HRESET and the standard
64-clock-wide HRESET.
0
= HRESET is 64 CLKx1 cycles wide
1
= HRESET is 1 pixel wide
HSFMT
1
= HRESET is 32 CLKx1 cycles wide
[6:2]
RW
00000
Reserved
These bits should only be written with a logical zero.
[1:0]
RW
00
VFILT
These bits control the number of taps in the Vertical Scaling Filter. The number
of taps must be chosen in conjunction with the horizontal scale factor to
ensure the needed data does not overflow the internal FIFO.
If the YCOMB bit in the VSCALE_HI register is a logical one, the following
settings and equations apply:
00*
= 2-tap
See Note 1.
01
= 3-tap
See Note 2.
10
= 4-tap
See Note 3.
11
= 5-tap
See Note 3.
If the YCOMB bit in the VSCALE_HI register is a logical zero, the following
settings and equations apply:
00*
= 2-tap interpolation only. See Note 1.
01
= 2-tap
and 2-tap interpolation. See Note 2.
10
= 3-tap
and 2-tap interpolation. See Note 3.
11
= 4-tap
and 2-tap interpolation.
See Note 3.
Note 1: Available at all resolutions.
Note 2: Only available if scaling to less than 385 horizontal active pixels
(CIF or smaller).
Note 3: Only available if scaling to less than 193 horizontal active pixels
(QCIF or smaller).
1
1
1
16
Z
1
–
+
(
)
2Z
1
–
Z
2
–
+
+
(
)
3Z
1
–
3Z
2
–
Z
3
–
+
+
+
(
)
1
4Z
1
–
6Z
2
–
4Z
3
–
Z
4
–
+
+
+
+
(
)
1
1
1
Z
1
–
+
(
)
2Z
1
–
Z
2
–
+
+
(
)
3Z
1
–
3Z
2
–
Z
3
–
+
+
+
(
)