
Brooktree
76
L848A_A
Bt848/848A/849A
Single-Chip Video Capture for PCI
E
LECTRICAL
I
NTERFACES
I
2
C Interface
An I
2
C write transaction consists of sending a START signal, 2 or 3 bytes of
data (checking for a receiver acknowledge after each byte), and a STOP signal. The
write data is supplied from a 24-bit register with bytes I2CDB0, I2CDB1, and
I2CDB2. This 24-bit register is shifted left to provide data serially, with the MSB
as the first bit. An I
2
C write occurs when the R/W bit in the I2CDB0[0] is set to a
logical low. The system driver can select to write 2 or 3 bytes of data by selecting
the appropriate value for I2CW3B bit.
An I
2
C read transaction consists of sending a START signal, 1 byte of data
(checking for a receiver acknowledge), reading 1 data byte from the slave, sending
the master NACK, and sending the STOP signal. The data read is shifted into the
I2CDB2 register. An I
2
C read occurs when the R/W bit in the I2CDB0[0] is set to
a logical one (Figure 36).
When the read or write operation is completed, Bt848 sends an interrupt over
the PCI bus to the host controller. The status bit RACK will indicate whether the
operation completed successfully with the correct number of slave acknowledges.
In the case where direct control of the I
2
C bus lines is desired, the Bt848 device
driver can disable the I
2
C hardware control and can take software control of the
SCL and SDA pins. This is useful in applications where the I
2
C bus is used for gen-
eral purpose I/O or if a special type of I
2
C operation (such as multi-mastering)
needs to be implemented.
For detailed information on the I
2
C bus, refer to
“The I
2
C-Bus Reference
Guide,”
reprinted by Brooktree.
Figure 36. I
2
C Typical Protocol Diagram
CHIP
ADDR
DATA
S
A
CHIP
ADDR
SUB
-
ADDR
8
BITS
S
A
A
A
P
DATA
D
ATA
R
EAD
D
ATA
W
RITE
F
ROM
B
T
848
TO
S
LAVE
F
ROM
S
LAVE
TO
B
T
848
NA
P
S
P
A
NA
=
START
=
STOP
=
ACKNOWLEDGE
=
NON
ACKNOWLEDGE