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參數(shù)資料
| 型號(hào)： | BT848A |
| 英文描述： | Single-Chip Video Capture for PCI |
| 中文描述： | 單芯片的PCI視頻捕捉 |
| 文件頁數(shù)： | 101/141頁 |
| 文件大?。?/td> | 1149K |
| 代理商： | BT848A |
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Brooktree
91
C
ONTROL
R
EGISTER
D
EFINITIONS
Device Status Register
L848A_A
Bt848/848A/849A
Single-Chip Video Capture for PCI
Device Status Register
Memory Mapped Location 0x000 – (DSTATUS)
Upon reset it is initialized to 0x00. COF is the least significant bit. The COF and LOF status bits hold their values until
reset to their default values by writing to them. The other six bits do not hold their values, but continually output the
status.
Bits
Type
Default
Name
Description
[7]
RW
0
PRES
Video Present Status. Video is determined as not present when an
input sync is not detected in 31 consecutive line periods.
0
= Video not present.
1
= Video present.
[6]
RW
0
HLOC
Device in H-lock. If HSYNC is found within
±
1 clock cycle of the
expected position of HSYNC for 32 consecutive lines, this bit is set
to a logical 1. Once set, if HSYNC is not found within
±
1 clock
cycle of the expected position of HSYNC for 32 consecutive lines,
this bit is set to a logical 0.
0
= Device not in H-lock.
1
= Device in H-lock.
[5]
RW
0
FIELD
Field Status. This bit reflects whether an odd or even field is being
decoded.
0
= Odd field.
1
= Even field.
[4]
RW
0
NUML
This bit identifies the number of lines found in the video stream.
This bit is used to determine the type of video input to the Bt848.
Thirty-two consecutive fields with the same number of lines is
required before this status bit will change.
0
= 525 line format (NTSC / PAL-M).
1
= 625 line format (PAL / SECAM).
[3]
RW
0
CSEL
Crystal Select. This bit identifies which crystal port is selected.
0
= XTAL0 input selected.
1
= XTAL1 input selected.
[2]
RW
0
Reserved
This bit must be set to zero.
PLOCK
A logical one indicates the PLL is out of lock. Once s/w has initial-
ized the PLL to run at the desired frequency, this bit should be read
and cleared until it is no longer set (up to 100 ms). Then the clock
input mode should be switched from xtal to PLL.
[1]
RW
0
LOF
Luma ADC Overflow. On power-up, this bit is set to 0. If an ADC
overflow occurs, the bit is set to a logical 1. It is reset after being
written to or a chip reset occurs.
[0]
RW
0
COF
Chroma ADC Overflow. On power-up, this bit is set to 0. If an ADC
overflow occurs, the bit is set to a logical 1. It is reset after being
written to or a chip reset occurs.
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