- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄366552 > AM8530 (Advanced Micro Devices, Inc.) Serial Communications Controller PDF資料下載
參數(shù)資料
| 型號(hào)： | AM8530 |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | Serial Communications Controller |
| 中文描述： | 串行通信控制器 |
| 文件頁數(shù)： | 91/194頁 |
| 文件大?。?/td> | 797K |
| 代理商： | AM8530 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁當(dāng)前第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁第187頁第188頁第189頁第190頁第191頁第192頁第193頁第194頁
Data Communication Modes Functional Description
AMD
4–39
The Tx Underrun/EOM status bit in RR0 will be set to ‘1’ to indicate that an underrun has
occurred, and that the CRC, or sync characters, have been loaded into the Transmit Shift
Register for transmission. The Low-to-High transition of this bit may be programmed to
generate an External/Status interrupt or, if interrupts are disabled, may be polled in RR0.
Hence, if the CRC check characters are to be properly appended to the end of a mes-
sage, the Reset Tx Underrun/EOM Command must be issued after the first, but before
the last, character is written to the Transmit Buffer.
Note that the Reset Tx Underrun/EOM command will not reset the status bit latch if the
Transmitter is disabled. However, if no External/Status interrupts are pending, or if a Re-
set External/Status Interrupt command accompanies this command while the transmitter
is disabled, an External/Status interrupt will be generated with the Tx Underrun/EOM bit
reset in RR0.
4.10.2.2.4
On the SCC, leading sync characters are automatically excluded from CRC calculation,
but it will be calculated on any sync characters sent as data unless the transmit CRC gen-
erator is disabled via bit D0 of WR5 when that character is loaded in the Transmit Shift
Register from the Transmit Buffer.
Tx CRC Character Exclusion
Internally, the CRC is enabled or disabled for a particular character at the same time as
the character is loaded from the Transmit Buffer to the Transmit Shift Register. Thus, to
exclude a character from CRC calculation, bit D0 of WR5 should be set to ‘0’ before the
character is written to the transmit buffer. This guarantees that the internal disable will
occur when the character moves from the buffer to the shift register. Once the buffer be-
comes empty, the Tx CRC Enable bit may be set for the next character.
4.10.2.3
The SCC can be used in applications where data are sent without enveloping them in any
specific protocol or Parity. This can be done by programming WR4 for the channel in Ex-
ternal SYNC mode as shown below.
Transparent Transmission
In this mode of operation, the transmitter will be configured for MONOSYNC operation
and the SYNC pin will be used to signal when to start reception of data. The transmitter is
initialized as before except that the first character to be sent must be written to WR6 be-
fore enabling the transmitter. Once the transmitter is enabled and transmission of the
character in WR6 has started, the Transmit Buffer can be written to with the next charac-
ter. From that point on, data from the Transmit Buffer will continue to be sent until the
transmitter is disabled. To prevent any unwanted data in WR6 from being sent when a
transmitter underrun occurs, the transmitter must be disabled during the transmission of
the last character. The same procedure is followed if another data block is to be sent.
0
0
1
1
0
0
X
0
WR4—Register Layout
Data reception in this mode of operation requires that the SYNC pin be used to signal
when character accumulation should commence at the receiver. As long as SYNC re-
mains Low data will continue to be received and transferred.
4.10.2.4
The SCC contains a transmitter-to-receiver synchronization function that may be used to
guarantee that the character boundaries for the received and transmitted data are the
same. In this mode the receiver is in Hunt and the transmitter is idle, sending either all
‘1’s or all ‘0’s. When the receiver recognizes a sync character, it leaves Hunt mode and
one character time later the transmitter is enabled and begins sending sync characters.
Transmitter to Receiver Synchronization
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM8530H | Serial Communications Controller |
| AM85C30-10PC | Enhanced Serial Communications Controller |
| Am85C30 | Serial Communications Controller |
| AM85C30 | Enhanced Serial Communications Controller |
| AM85C30-8PC | Enhanced Serial Communications Controller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM8530ADC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Communications Controller |
| AM8530ADCB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Communications Controller |
| AM8530AJC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Communications Controller |
| AM8530APC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Communications Controller |
| AM8530DC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Communications Controller |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。