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參數(shù)資料
| 型號(hào)： | AM8530 |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | Serial Communications Controller |
| 中文描述： | 串行通信控制器 |
| 文件頁(yè)數(shù)： | 103/194頁(yè) |
| 文件大小： | 797K |
| 代理商： | AM8530 |
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Support Circuitry Programming
AMD
5–9
5.3.3
Initializing the BRG is done in four steps. First, the time-constant is determined and
loaded into WR12 and WR13. Next, the processor must select the clock source for the
BRG by writing to bit D1 of WR14. Finally, the BRG is enabled by setting bit D0 of WR14
to ‘1’. Note that the first write to WR14 is not necessary after a hardware reset if the clock
source is to be the
RTxC
pin. This is because a hardware reset automatically selects the
RTxC
pin as the BRG clock source.
BRG Initialization
5.4
The SCC provides four data encoding methods, selected by bits D6 and D5 in WR10. An
example of these four methods is shown in Figure 5–4. Encoding may be used for asyn-
chronous or synchronous data as long as the clock mode is x1. Note that the data encod-
ing method selected is active even though the transmitter or receiver may be idling or dis-
abled.
DAT A ENCODING/DECODING
1
1
0
0
1
0
Data
NRZ
NRZI
FM1
(BiPhase Mark)
FM0
(BiPhase Space)
Bit Cell Level:
High = 1
Low = 0
No Change = 1
Change = 0
Bit Center Transition:
Transition = 1
No Transition = 0
Manchester
No Transition = 1
Transition = 0
High
→
Low = 1
Low
→
High = 0
Figure 5–4. Data Encoding
5.4.1
In NRZ encoding a ‘1’ is represented by a High level and a ‘0’ is represented by a Low
level. In this encoding method only a minimal amount of clocking information is available
in the data stream in the form of transitions on bit-cell boundaries. In an arbitrary data
pattern this may not be sufficient to generate a clock for the data from the data itself.
NRZ (Non-Return to Zero)
5.4.2
In NRZI encoding a ‘1’ is represented by no change in the level and a ‘0’ is represented
by a change in the level. As in NRZ only a minimal amount of clocking information is
available in the data stream, in the form of transitions on bit cell boundaries. In an arbi-
trary data pattern this may not be sufficient to generate a clock for the data from the data
itself. In the case of SDLC Mode operation, where the number of consecutive ‘1’s in the
data stream is limited, a minimum number of transitions to generate a clock are guar-
anteed.
NRZI (Non-Return to Zero Inverted)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM8530H | Serial Communications Controller |
| AM85C30-10PC | Enhanced Serial Communications Controller |
| Am85C30 | Serial Communications Controller |
| AM85C30 | Enhanced Serial Communications Controller |
| AM85C30-8PC | Enhanced Serial Communications Controller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM8530ADC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Communications Controller |
| AM8530ADCB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Communications Controller |
| AM8530AJC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Communications Controller |
| AM8530APC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Communications Controller |
| AM8530DC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Communications Controller |
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