參數(shù)資料
型號: AM8530
廠商: Advanced Micro Devices, Inc.
英文描述: Serial Communications Controller
中文描述: 串行通信控制器
文件頁數(shù): 116/194頁
文件大小: 797K
代理商: AM8530
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁當前第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁第187頁第188頁第189頁第190頁第191頁第192頁第193頁第194頁
Register Description
AMD
6–6
Bits D7 and D6: CRC Reset Codes 0 and 1
Null code (00)
. This command has no effect on the SCC and is used when a write to
WR0 is necessary for some reason other than a CRC Reset command.
Reset Receive CRC Checker (01)
. This command is used to initialize the receive CRC
circuitry. It is necessary in synchronous modes (except SDLC) if the Enter Hunt Mode
command in Write Register 3 is not issued between received messages. Any action that
disables the receiver initializes the CRC circuitry. Also, whenever the receiver is in Hunt
mode, or whenever a flag is received, the CRC checker will be automatically reset in
SDLC mode.
Reset Transmit CRC Generator (10)
. This command initializes the CRC generator. It is
usually issued in the initialization routine and after the CRC has been transmitted. A
Channel Reset will not initialize the generator and this command should not be issued
until after the transmitter has been enabled in the initialization routine.
Reset Transmit Underrun/EOM Latch (11)
. This command controls the transmission of
CRC at the end of transmission (EOM). If this latch has been reset, and a transmit under-
run occurs, the SCC automatically appends CRC to the message. In SDLC mode with
Abort on Underrun selected, the SCC sends an abort, and Flag on underrun if the TX Un-
derrun/EOM latch has been reset.
At the start of the CRC transmission the Tx Underrun/EOM latch is set. The Reset com-
mand can be issued at any time during a message. If the transmitter is disabled this com-
mand will not reset the latch. However, if no External Status interrupt is pending, or if a
Reset External Status Interrupt command accompanies this command while the transmit-
ter is disabled, an External/Status interrupt is generated with the Tx Underrun/EOM bit
reset in RRO.
Bits D5–D3: Command Codes
Null Code (000)
. The Null command has no effect on the SCC.
Point High (001)
. This command effectively adds eight to the Register Pointer (D2–D0)
by allowing WR8 through WR15 to be accessed. The Point High command and the Reg-
ister Pointer bits are written simultaneously.
Reset External/Status Interrupts (010)
. After an External/Status interrupt (a change on
a modem line or a break condition, for example), the status bits in RR0 are latched. This
command enables the bits and allows interrupts to occur again as a result of a status
change. Latching the status bits captures short pulses until the CPU has time to read the
change. The SCC contains simple queuing logic associated with most of the external
status bits in RR0. If another External/Status condition changes while a previous condi-
tion is still pending (Reset External/Status Interrupts has not yet been issued) and this
condition persists until after the command is issued, this second change causes another
External/Status interrupt. However, if this second status change does not persist (there
are two transitions), another interrupt is not generated. Exceptions to this rule are detailed
in the RR0 description.
Send Abort (011)
. This command is used in SDLC mode to transmit a sequence of eight
to thirteen ‘1s.’ This command always empties the transmit buffer and sets Tx Underrun/
EOM bit in Read Register 0.
Enable Interrupt on Next RX Character (100)
. If the interrupt on the First Received
Character mode is selected, this command is used to reactivate that mode after each
message is received. The next character to enter the receive FIFO causes a Receive
interrupt. Alternatively, the first previously stored character in the FIFO will cause a Re-
ceive interrupt.
Reset Tx Interrupt Pending (101)
. This command is used in cases where there are no
more characters to be sent; e.g., at the end of a message. This command prevents fur-
ther transmit interrupts until after the next character has been loaded into the transmit
相關PDF資料
PDF描述
AM8530H Serial Communications Controller
AM85C30-10PC Enhanced Serial Communications Controller
Am85C30 Serial Communications Controller
AM85C30 Enhanced Serial Communications Controller
AM85C30-8PC Enhanced Serial Communications Controller
相關代理商/技術參數(shù)
參數(shù)描述
AM8530ADC 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Communications Controller
AM8530ADCB 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Communications Controller
AM8530AJC 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Communications Controller
AM8530APC 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Communications Controller
AM8530DC 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Communications Controller