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參數(shù)資料
| 型號(hào)： | AM8530 |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | Serial Communications Controller |
| 中文描述： | 串行通信控制器 |
| 文件頁(yè)數(shù)： | 127/194頁(yè) |
| 文件大?。?/td> | 797K |
| 代理商： | AM8530 |
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Register Description
AMD
6–17
6.2.8
Write Register 7 (S ync Charac ter or S DLCFlag/S DLC
Option Register)
Note S DLC option register is available only in CMOS version.
In the Nmos Am8530H, the use of this register differs depending on the mode the SCC is
programmed in. In Monosync mode, WR7 is programmed with the receive sync charac-
ter; in BISYNC, it is programmed with the second byte (the last 8 bits) of the 16-bit sync
character. In SDLC modes, WR7 is programmed with the flag character (01111110).
Note, however, that WR7 may hold the receive sync character or flag if one of the special
versions of the External Sync mode is selected.
Write Register 7
′
(S pec ial S DLC Enhanc ement Register)
In the CMOS Am8530, special SDLC options are provided that enable the user to more
effectively interface to the Am85C30. These options are available to the user if the previ-
ously unused bit, D0 of WR15, is set to ‘1’. When this bit is set, and the SCC is pro-
grammed for SDLC operation, an access to WR7 accesses a different register which
allows the programming of these options. This register is referred to as WR7’ (WR7
prime). Resetting this bit (D0 of WR15) disables the options and the next access to WR7
is to the flag register. Therefore, the user should always program the flag character first
before setting bit D0 of WR15 to ‘1’. This register is readable by executing a read to RR14
when D0 of WR15 and D6 of WR7’ are set to ‘1’.
Note that WR7 is not used in Asynchronous mode. Bit positions for WR7 are shown in
Figure 6–8. Bit positions for WR7’ are shown in Figure 6–9 with bit descriptions given
below.
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
TxD forced high in SDLC NRZI Mode
DTR/REQ Timing Mode
Receive CRC
Extended Read Enable
Auto Tx Flag
Auto EOM Reset
Auto RTS Deactivation
This bit must always be programmed with a ‘0’
Figure 6–9. Write Register 7
′
Bit 7: Not used. This bit must be programmed with ‘0’.
Bit 6: Extended Read Enable
If this bit is set to ‘1’ the user is able to read the following previously unreadable registers;
WR3, WR4, WR5 and WR10 in the CMOS SCC in each channel. These registers are
read by addressing bogus read registers RR9, RR4, RR5 and RR11, respectively.
WR7’ is updated or modified by writing to WR7 while this bit is set and is read by execut-
ing a read cycle to WR14 (RR14).
Bit 5: Receive CRC
If this bit is set to ‘1’, the last two bits of the received CRC are properly clocked into the
receive shift register and are available to the user.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM8530H | Serial Communications Controller |
| AM85C30-10PC | Enhanced Serial Communications Controller |
| Am85C30 | Serial Communications Controller |
| AM85C30 | Enhanced Serial Communications Controller |
| AM85C30-8PC | Enhanced Serial Communications Controller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM8530ADC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Communications Controller |
| AM8530ADCB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Communications Controller |
| AM8530AJC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Communications Controller |
| AM8530APC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Communications Controller |
| AM8530DC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Communications Controller |
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