- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄366552 > AM8530 (Advanced Micro Devices, Inc.) Serial Communications Controller PDF資料下載
參數(shù)資料
| 型號(hào)： | AM8530 |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | Serial Communications Controller |
| 中文描述： | 串行通信控制器 |
| 文件頁(yè)數(shù)： | 46/194頁(yè) |
| 文件大?。?/td> | 797K |
| 代理商： | AM8530 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)當(dāng)前第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)第174頁(yè)第175頁(yè)第176頁(yè)第177頁(yè)第178頁(yè)第179頁(yè)第180頁(yè)第181頁(yè)第182頁(yè)第183頁(yè)第184頁(yè)第185頁(yè)第186頁(yè)第187頁(yè)第188頁(yè)第189頁(yè)第190頁(yè)第191頁(yè)第192頁(yè)第193頁(yè)第194頁(yè)
I/O Programming Functional Description
AMD
3–15
3.8.4
The Tx Underrun/EOM status bit is used in SDLC and Synchronous modes of operation
to control the transmission of CRC characters. This bit is set to ‘1’ when the Transmit
Buffer and Transmit Shift Register go empty and is reset to ‘0’ by issuing the Reset
Transmit Underrun/EOM command in WR0. Only the Low-to-High transition of this bit will
cause the latches to close and, if the Tx Underrun/EOM IE bit in WR15 (D6) is set to ‘1’,
cause an External/Status Interrupt to be generated.
T x Underrun/EOM
This status bit is always set to ‘1’ in Asynchronous mode unless a Reset Transmit Under-
run/EOM command is erroneously issued. In this case, the Send Abort Command can be
used to set this bit to ‘1’ and, at the same time, cause an External/Status Interrupt.
Note that this bit will be set to ‘1’ when either of the following occurs; 1) a Send Abort
command is issued, 2) the transmitter is disabled, or 3) a Channel or Hardware Reset is
executed.
3.8.5
The
CTS
Status bit reports the state of the
CTS
input pin the last time any of the enabled
External/Status bits changed. Any transition on the
CTS
pin, while no other interrupts are
pending, latches the state of the
CTS
pin and generates an External/Status interrupt if the
CTS
IE bit in WR15 is set to ‘1’. However, only an odd number of transitions on the
CTS
pin while another External/Status is pending will cause an External/Status interrupt after
the Reset External/Status Interrupt command is issued.
Clear to S end
If the
CTS
IE bit is reset, the
CTS
status merely reports the current inverted unlatched
state of the
CTS
pin; that is, if the
CTS
pin is Low, the
CTS
status bit will be High.
Note that after the Reset External/Status Interrupt command is issued, if the latches were
closed, they will close again if there was an odd number of transitions on the
CTS
pin;
they will remain open if there was an even number of transitions on the input pin.
3.8.6
The DCD Status bit reports the state of the
DCD
input pin the last time any of the enabled
External/Status bits changed. Any transition on the
DCD
pin, while no other interrupts are
pending, latches the state of the
DCD
pin and generates an External/Status interrupt if
the DCD IE bit in WR15 is set to ‘1’. However, only an odd number of transitions on the
DCD
pin while another External/Status is pending will cause an External/Status interrupt
after the Reset External/Status Interrupt command is issued.
Data Carrier Detec t
If the DCD IE bit is reset, the DCD status merely reports the current inverted unlatched
state of the DCD pin; that is, if the
DCD
pin is Low, the DCD status bit will be High.
Note that after the Reset External/Status Interrupt command is issued, if the latches were
closed, they will close again if there was an odd number of transitions on the
DCD
pin;
they will remain open if there was an even number of transitions on the input pin.
If careful attention is paid to details, the interrupt service routine for External/Status inter-
rupts is straightforward. To determine which bit or bits changed state, the routine should
first read RR0 and compare it to a copy from memory. For each changed bit, the appro-
priate action should be taken and the copy in memory updated. The service routine
should close with a Reset External/Status Interrupts command to re-open the latches.
The copy of RR0 in memory should always have the Zero Count bit set to ‘0’, since this
will be the state of the bit after the Reset External/Status Interrupts command at the end
of the service routine.
3.9
The SCC offers several alternatives for the block transfer of data. The various options are
selected via WR1 and WR14 as follows.
BLOCK T RANS FERS
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM8530H | Serial Communications Controller |
| AM85C30-10PC | Enhanced Serial Communications Controller |
| Am85C30 | Serial Communications Controller |
| AM85C30 | Enhanced Serial Communications Controller |
| AM85C30-8PC | Enhanced Serial Communications Controller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM8530ADC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Communications Controller |
| AM8530ADCB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Communications Controller |
| AM8530AJC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Communications Controller |
| AM8530APC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Communications Controller |
| AM8530DC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Communications Controller |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。