參數(shù)資料
型號(hào)： AM79C970
廠商： Advanced Micro Devices, Inc.
英文描述： PCnetTM-PCI Single-Chip Ethernet Controller for PCI Local Bus
中文描述： PCnetTM - PCI單芯片以太網(wǎng)控制器的PCI總線
文件頁(yè)數(shù)： 88/168頁(yè)
文件大?。?/td> 943K
代理商： AM79C970
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P R E L I M I N A R Y
AMD
1-955
Am79C970
initialization
completed.
INIT is set by writing a “1”. Writing
a “0” has no effect. INIT is cleared
by H_RESET, S_RESET or by
setting the STOP bit.
sequence
has
CSR1: IADR[15:0]
Bit
Name
Description
31–16
RES
Reserved locations. Written as
ZEROs and read as undefined.
Lower 16 bits of the address of
the Initialization Block. Bit loca-
tions 1 and 0 must both be ZERO
to align the initialization block to a
double-word boundary, regard-
less of the value of SSIZE32
(BCR20/CSR58, bit 8).
This register is aliased with
CSR16.
Read/Write
accessible
when the STOP bit in CSR0 is
set. Unaffected by H_RESET or
S_RESET or by setting the
STOP bit.
15–0 IADR[15:0]
only
CSR2: IADR[31:16]
Bit
Name
Description
31–16
RES
Reserved locations. Written as
ZEROs and read as undefined.
IADR[31:24] If SSIZE32 is set (BCR20, bit 8),
then the IADR[31:24] bits will be
used strictly as the upper 8 bits of
the initialization block address.
However, if SSIZE32 is reset
(BCR20,
IADR[31:24] bits will be used to
generate the upper 8 bits of all
bus mastering addresses, as re-
quired for a 32 bit address bus.
Note that the 16-bit software
structures specified by the
SSIZE32=0 setting will yield only
24 bits of address for PCnet-PCI
bus master accesses, while the
32-bit hardware for which the
PCnet-PCI controller is intended
will require 32 bits of address.
Therefore,
SSIZE32=0, the IADR[31:24] bits
will be appended to the 24-bit in-
itialization address, to each
24-bit descriptor base address
and to each beginning 24-bit
buffer address in order to form
complete 32-bit addresses. The
upper 8 bits that exist in the de-
scriptor address registers and
15–8
bit
8),
then
the
whenever
the buffer address registers
which are stored on board the
PCnet-PCI controller will be
overwritten with the IADR[31:24]
value, so that CSR accesses to
these registers will show the 32
bit address that includes the ap-
pended field.
If SSIZE32=1, then software will
provide 32-bit pointer values for
all of the shared software struc-
tures – i.e. descriptor bases and
buffer addresses, and therefore,
IADR[31:24] will not be written to
the upper 8 bits of any of these
resources, but it will be used as
the upper 8 bits of the initializa-
tion address.
This register is aliased with
CSR17.
Read/Write
accessible
when the STOP bit in CSR0 is
set. Unaffected by H_RESET,
S_RESET or by setting the
STOP bit.
Bits 23 through 16 of the address
of the Initialization Block. When-
ever this register is written,
CSR17 is updated with CSR2’s
contents.
Read/Write
accessible
when the STOP bit in CSR0 is
set. Unaffected by H_RESET,
S_RESET or by setting the
STOP bit.
only
7–0 IADR[23:16]
only
CSR3: Interrupt Masks and Deferral Control
Bit
Name
Description
31–16
RES
Reserved locations. Written as
ZEROs and read as undefined.
Reserved location. Read and
written as ZERO.
Babble Mask. If BABLM is set,
the BABL bit in CSR0 will be
masked and unable to set INTR
flag in CSR0.
Read/Write accessible always.
BABLM is cleared by H_RESET
or S_RESET and is not affected
by STOP.
Reserved location. Read and
written as ZERO.
Missed Frame Mask. If MISSM is
set, the MISS bit in CSR0 will be
masked and unable to set INTR
flag in CSR0.
Read/Write accessible always.
MISSM is cleared by H_RESET
15
RES
14
BABLM
13
RES
12
MISSM
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AM79C970A 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
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