參數(shù)資料
型號： AM79C970
廠商： Advanced Micro Devices, Inc.
英文描述： PCnetTM-PCI Single-Chip Ethernet Controller for PCI Local Bus
中文描述： PCnetTM - PCI單芯片以太網(wǎng)控制器的PCI總線
文件頁數(shù)： 122/168頁
文件大?。?/td> 943K
代理商： AM79C970
P R E L I M I N A R Y
AMD
1-989
Am79C970
Initialization Block
When SSIZE32=0 (BCR20, bit 8), then the software
structures are defined to be 16 bits wide. The base ad-
dress of the Initialization block in this mode must be
aligned to a WORD boundary, i.e. CSR1, bit 0 and
CSR16, bit 0 must be set to ZERO. When SSIZE32 = 0,
the initialization block looks like Table 13.
Note that the PCnet-PCI device performs DWORD ac-
cesses to read the initialization block. This statement is
always true, regardless of the setting of the SSIZE32 bit.
When SSIZE32=1 (BCR20, bit 8), then the software
structures are defined to be 32 bits wide. The base ad-
dress of the Initialization block in this mode must be
aligned to a DOUBLE WORD boundary, i.e., CSR1, bits
0 and 1 and CSR16, bits 0 and 1 must be set to ZERO.
When SSIZE32 = 1, the initialization block looks like
Table 14.
Table 13. 16-Bit Data Structure Initialization Block
Address
IADR+00h
IADR+02h
IADR+04h
IADR+06h
IADR+08h
IADR+0Ah
IADR+0Ch
IADR+0Eh
IADR+10h
IADR+12h
IADR+14h
IADR+16h
Bits 15–13
Bit 12
Bits 11–8
MODE 15–00
PADR 15–00
PADR 31–16
PADR 47–32
LADRF 15–00
LADRF 31–16
LADRF 47–32
LADRF 63–48
RDRA 15–00
RES
TDRA 15–00
RES
Bits 7–4
Bits 3–0
RLEN
0
RDRA 23–16
TLEN
0
TDRA 23–16
Table 14. 32-Bit Data Structure Initialization Block
Bits
31–28
TLEN
Bits
27–24
RES
Bits
23–20
RLEN
Bits
19–16
RES
Bits
15–12
Bits
11–8
Bits
7–4
Bits
3–0
Address
IADR+00h
IADR+04h
IADR+08h
IADR+0Ch
IADR+10h
IADR+14h
IADR+18h
MODE
PADR 31–00
RES
PADR 47–32
LADR 31–00
LADR 63–32
RDRA 31–00
TDRA 31–00
RLEN and TLEN
When SSIZE32=0 (BCR20, bit 8), then the software
structures are defined to be 16 bits wide, and the RLEN
and TLEN fields in the initialization block are 3 bits wide,
occupying bits 15, 14, and 13, and the value in these
fields determines the number of Receive and Transmit
Descriptor Ring Entries (DRE) which are used in the de-
scriptor rings. Their meaning is as follows:
R/TLEN
000
001
010
011
100
101
110
111
# of DREs
1
2
4
8
16
32
64
128
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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