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參數(shù)資料
| 型號： | AM79C970 |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | PCnetTM-PCI Single-Chip Ethernet Controller for PCI Local Bus |
| 中文描述： | PCnetTM - PCI單芯片以太網(wǎng)控制器的PCI總線 |
| 文件頁數(shù)： | 152/168頁 |
| 文件大?。?/td> | 943K |
| 代理商： | AM79C970 |
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1-1019
Am79C970
Recommendation for Power and Ground
Decoupling
APPENDIX B
The mixed analog/digital circuitry in the PCnet-PCI
make it imperative to provide noise-free power and
ground connections to the device. Without clean power
and ground connections, a design may suffer from high
bit error rates or may not function at all. Hence, it is
highly recommended that the guidelines presented here
are followed to ensure a reliable design.
Decoupling/Bypass Capacitors: Adequate decoupling
of the power and ground pins and planes is required by
all PCnet-PCI designs. This includes both low-fre-
quency bulk capacitors and high frequency capacitors.
It is recommended that
at least one
low-frequency bulk
(e.g. 22
μ
F) decoupling capacitor be used in the area of
the PCnet-PCI device. The bulk capacitor(s) should be
connected directly to the power and ground planes. In
addition,
at least 8
high frequency decoupling capaci-
tors (e.g. 0.1
μ
F multilayer ceramic capacitors) should
be used around the periphery of the PCnet-PCI device
to prevent power and ground bounce from affecting de-
vice operation. To reduce the inductance between the
power and ground pins and the capacitors, the pins
should be connected directly to the capacitors, rather
than through the planes to the capacitors. The sug-
gested connection scheme for the capacitors is shown
in the figure below. Note also that the traces connecting
these pins to the capacitors should be as wide as possi-
ble to reduce inductance (15 mils is desirable).
18220C-54
V
DD
/V
DDB
V
SS
/V
SSB
C
A
P
PCnet
V
DD
/V
DDB
V
SS
/V
SSB
C
A
P
PCnet
C
A
P
PCnet
Correct
Correct
Incorrect
Via to the Power Plane
Via to the Ground Plane
V
DD
/V
DDB
V
SS
/V
SSB
The most critical pins in the layout of a PCnet-PCI
design are the 4 analog power and 2 analog ground
pins, AVDD[1–4] and AVSS[1–2], respectively. All of
these pins are located in one corner of the device, the
“analog corner.” Specific functions and layout require-
ments of the analog power and ground pins are given
below.
AVSS1 and AVDD3: These pins provide the power and
ground for the Twisted Pair and AUI drivers. In addition
AVSS1 serves as the ground for the logic interfaces in
the 20 MHz Crystal Oscillator. Hence, these pins can be
very noisy. A dedicated 0.1
μ
F capacitor between these
pins is recommended.
AVSS2 and AVDD2: These pins are the
most critical
pins on the PCnet-PCI device because they provide the
power and ground for the phase-lock loop (PLL) portion
of the chip. The voltage-controlled oscillator (VCO)
portion of the PLL is sensitive to noise in the 60 kHz –
200 kHz. range. To prevent noise in this frequency
range from disrupting the VCO, it is
strongly recom-
mended
that the low-pass filter shown below be imple-
mented on these pins.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C970A | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
| AM79C970AKC | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
| AM79C970AKC\\W | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Advanced Micro Devices 功能描述: |
| AM79C970AKC\W | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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