
P R E L I M I N A R Y
AMD
1-935
Am79C970
Table 7 describes all possible bus slave accesses that
may be directed toward the PCnet-PCI controller. (i.e.,
the PCnet-PCI controller is the target device during the
transfer.) The first column indicates the type of slave ac-
cess. RD stands for READ, WR for a WRITE operation.
The second column indicates the value of the C/
BE
[3:0]
lines during the data phase of the transfer. The four byte
columns (AD[31:24], AD[23:16], AD[15:8], AD[7:0]) in-
dicate the value on the address/data bus during the data
phase of the access. “data” indicates the position of the
active bytes; “copy” indicates the positions of copies of
the active bytes; “undef” indicates byte locations that are
undefined during the transfer.
Table 7. Bus Slave Accesses
AD
AD
AD
[15:8]
AD
[7:0]
TYPE
BE
[3:0]
[31:24]
[23:16]
Comments
RD
0000
data
data
data
data
DWORD access to DWORD address, e.g. 300h,
30Ch, 310h (DWIO mode only)
RD
1100
undef
undef
data
data
word access to even word address, e.g. 300h,
30Ch, 310h (WIO mode only)
RD
0011
data
data
copy
copy
word access to odd word address, e.g. 302h, 30Eh,
312h (WIO mode only)
RD
1110
undef
undef
undef
data
byte access to lower byte of even word address, e.g.
300h, 304h (WIO mode only, APROM accesses
only)
RD
1101
undef
undef
data
undef
byte access to upper byte of even word address,
e.g. 301h, 305h (WIO mode only, APROM accesses
only)
RD
1011
undef
data
undef
copy
byte access to lower byte of odd word address, e.g.
302h, 306h (WIO mode only, APROM accesses
only)
RD
0111
data
undef
copy
undef
byte access to upper byte of odd word address, e.g.
303h, 307h (WIO mode only, APROM accesses
only)
WR
0000
data
data
data
data
DWORD access to DWORD address, e.g. 300h,
30Ch, 310h (DWIO mode only)
WR
1100
undef
undef
data
data
word access to even word address, e.g. 300h,
30Ch, 310h (WIO mode only)
WR
0011
data
data
undef
undef
word access to odd word address, e.g. 302h, 30Eh,
312h (WIO mode only)
EEPROM Microwire Access
The PCnet-PCI controller contains a built-in capability
for reading and writing to an external EEPROM. This
built-in capability consists of a Microwire interface for di-
rect connection to a Microwire compatible EEPROM, an
automatic EEPROM read feature, and a user-program-
mable register that allows direct access to the Microwire
interface pins.
Automatic EEPROM Read Operation
Shortly after the deassertion of the
RST
pin, the PCnet-
PCI controller will read the contents of the EEPROM
that is attached to the Microwire interface. Because of
this automatic-read capability of the PCnet-PCI control-
ler, an EEPROM can be used to program many of the
features of the PCnet-PCI controller at power-up, allow-
ing system-dependent configuration information to be
stored in the hardware, instead of inside of oper-
atingcode.
If an EEPROM exists on the Microwire interface, the
PCnet-PCI controller will read the EEPROM contents at
the end of the H_RESET operation. The EEPROM con-
tents will be serially shifted into a temporary register and
then sent to various register locations on board the
PCnet-PCI controller. The host can access the PCI Con-
figuration Space during the EEPROM read operations.
Access to the PCnet-PCI I/O resources, however, is not
possible during the EEPROM read operation. The
PCnet-PCI controller will terminate these I/O accesses
with the assertion of
DEVSEL
and
STOP
while
TRDY
is
not asserted, signaling to the initiator to retry the access
at a later time.
A checksum verification is performed on the data that is
read from the EEPROM. If the checksum verification of
the EEPROM data fails, then at the end of the EEPROM
read sequence, the PCnet-PCI controller will force all
EEPROM-programmable BCR registers back to their