- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄366550 > AM79C970 (Advanced Micro Devices, Inc.) PCnetTM-PCI Single-Chip Ethernet Controller for PCI Local Bus PDF資料下載
參數(shù)資料
| 型號： | AM79C970 |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | PCnetTM-PCI Single-Chip Ethernet Controller for PCI Local Bus |
| 中文描述： | PCnetTM - PCI單芯片以太網(wǎng)控制器的PCI總線 |
| 文件頁數(shù)： | 15/168頁 |
| 文件大?。?/td> | 943K |
| 代理商： | AM79C970 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁當(dāng)前第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁
AMD
P R E L I M I N A R Y
1-882
Am79C970
PIN DESCRIPTION
PCI Interface
AD[31:00]
Address and Data Input/Output
These signals are multiplexed on the same PCI pins.
During the first clock of a transaction AD[31:00] contain
the physical byte address (32 bits). During the subse-
quent clocks AD[31:00] contain data. Byte ordering is lit-
tle endian by default. AD[07:00] are defined as least
significant byte and AD[31:24] are defined as the most
significant byte. For FIFO data transfers, the PCnet-PCI
controller can be programmed for big endian byte order-
ing. See CSR3, bit 2 (BSWP) for more details.
During the address phase of the transaction, when the
PCnet-PCI controller is a bus master, AD[31:2] will ad-
dress the active DWORD (double-word). The PCnet-
PCI controller always drives AD[1:0] to ’00’ during the
address phase indicating linear burst order. When the
PCnet-PCI controller is not a bus master, the AD[31:00]
lines are continuously monitored to determine if an ad-
dress match exists for I/O slave transfers.
During the data phase of the transaction, AD[31:00] are
driven by the PCnet-PCI controller when performing bus
master writes and slave read operations. Data on
AD[31:00] is latched by the PCnet-PCI controller when
performing bus master reads and slave write
operations.
When
RST
is active, AD[31:0] are inputs for NAND tree
testing.
C/
BE
[3:0]
Bus Command and Byte Enables
Input/Output
These signals are multiplexed on the same PCI pins.
During the address phase of the transaction, C/
BE
[3:0]
define the bus command. During the data phase
C/
BE
[3:0] are used as Byte Enables. The Byte Enables
define which physical byte lanes carry meaningful data.
C/
BE
0 applies to byte 0 (AD[07:00]) and C/
BE
3 applies
to byte 3 (AD[31:24]). The function of the Byte Enables
is independent of the byte ordering mode (CSR3, bit 2).
When
RST
is active, C/
BE
[3:0] are inputs for NAND tree
testing.
CLK
Clock
Input
This signal provides timing for all the transactions on the
PCI bus and all PCI devices on the bus including the
PCnet-PCI controller. All bus signals are sampled on the
rising edge of CLK and all parameters are defined with
respect to this edge. The PCnet-PCI controller operates
over a range of 0 to 33 MHz.
When
RST
is active, CLK is an input for NAND tree
testing.
DEVSEL
Device Select
Input/Output
This signal when actively driven by the PCnet-PCI con-
troller as a slave device signals to the master device that
the PCnet-PCI controller has decoded its address as the
target of the current access. As an input it indicates
whether any device on the bus has been selected.
When
RST
is active,
DEVSEL
is an input for NAND tree
testing.
FRAME
Cycle Frame
Input/Output
This signal is driven by the PCnet-PCI controller when it
is the bus master to indicate the beginning and duration
of the access.
FRAME
is asserted to indicate a bus
transaction is beginning.
FRAME
is asserted while data
transfers continue.
FRAME
is deasserted when the
transaction is in the final data phase.
When
RST
is active,
FRAME
is an input for NAND tree
testing.
GNT
Bus Grant
Input
This signal indicates that the access to the bus has been
granted to the PCnet-PCI controller.
The PCnet-PCI controller supports bus parking. When
the PCI bus is idle and the system arbiter asserts
GNT
without an active
REQ
from the PCnet-PCI controller,
the PCnet-PCI controller will actively drive the AD, C/
BE
and PAR lines.
When
RST
is active,
GNT
is an input for NAND tree
testing.
IDSEL
Initialization Device Select
Input
This signal is used as a chip select for the PCnet-PCI
controller during configuration read and write
transaction.
When
RST
is active, IDSEL is an input for NAND tree
testing.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM79C971VCW | PCnet⑩-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus |
| AM79C971 | PCnet⑩-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus |
| AM79C971KCW | IC LOGIC 16211 24-BIT FET BUS SWITCH -40+85C TSSOP-56 35/TUBE |
| AM79C972BKCW | PCnet⑩-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support |
| AM79C972BKIW | PCnet⑩-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C970A | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
| AM79C970AKC | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
| AM79C970AKC\\W | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Advanced Micro Devices 功能描述: |
| AM79C970AKC\W | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。