- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄366550 > AM79C970 (Advanced Micro Devices, Inc.) PCnetTM-PCI Single-Chip Ethernet Controller for PCI Local Bus PDF資料下載
參數(shù)資料
| 型號(hào)： | AM79C970 |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | PCnetTM-PCI Single-Chip Ethernet Controller for PCI Local Bus |
| 中文描述： | PCnetTM - PCI單芯片以太網(wǎng)控制器的PCI總線 |
| 文件頁(yè)數(shù)： | 51/168頁(yè) |
| 文件大?。?/td> | 943K |
| 代理商： | AM79C970 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)當(dāng)前第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)
AMD
P R E L I M I N A R Y
1-918
Am79C970
Receive Descriptor Table Entry (RDTE)
If the PCnet-PCI controller does not own both the cur-
rent and the next Receive Descriptor Table Entry then
the PCnet-PCI controller will continue to poll according
to the polling sequence described above. If the receive
descriptor ring length is 1, then there is no next descrip-
tor to be polled.
If a poll operation has revealed that the current and the
next RDTE belong to the PCnet-PCI controller then ad-
ditional poll accesses are not necessary. Future poll op-
erations will not include RDTE accesses as long as the
PCnet-PCI controller retains ownership of the current
and the next RDTE.
When receive activity is present on the channel, the
PCnet-PCI controller waits for the complete address of
the message to arrive. It then decides whether to accept
or reject the frame based on all active addressing
schemes. If the frame is accepted the PCnet-PCI con-
troller checks the current receive buffer status register
CRST (CSR41) to determine the ownership of the cur-
rent buffer.
If ownership is lacking, then the PCnet-PCI controller
will immediately perform a (last ditch) poll of the current
RDTE. If ownership is still denied, then the PCnet-PCI
controller has no buffer in which to store the incoming
message. The MISS bit will be set in CSR0 and an inter-
rupt will be generated if IENA=1 (CSR0) and MISSM=0
(CSR3). Another poll of the current RDTE will not occur
until the frame has finished.
If the PCnet-PCI controller sees that the last poll (either
a normal poll, or the last-ditch effort described in the
above paragraph) of the current RDTE shows valid own-
ership, then it proceeds to a poll of the next RDTE. Fol-
lowing this poll, and regardless of the outcome of this
poll, transfers of receive data from the FIFO may begin.
Regardless of ownership of the second receive descrip-
tor, the PCnet-PCI controller will continue to perform re-
ceive data DMA transfers to the first buffer. If the frame
length exceeds the length of the first buffer, and the
PCnet-PCI controller does not own the second buffer,
ownership of the current descriptor will be passed back
to the system by writing a ZERO to the OWN bit of
RMD1 and status will be written indicating buffer
(BUFF=1) and possibly overflow (OFLO=1) errors.
If the frame length exceeds the length of the first (cur-
rent) buffer, and the PCnet-PCI controller does own the
second (next) buffer, ownership will be passed back to
the system by writing a ZERO to the OWN bit of RMD1
when the first buffer is full. Receive data transfers to the
second buffer may occur before the PCnet-PCI control-
ler proceeds to look ahead to the ownership of the third
buffer. Such action will depend upon the state of the
FIFO when the status has been updated on the first de-
scriptor. In any case, lookahead will be performed to the
third buffer and the information gathered will be stored in
the chip, regardless of the state of the ownership bit. As
in the transmit flow, lookahead operations are per-
formed only once.
This activity continues until the PCnet-PCI controller
recognizes the completion of the frame (the last byte of
this receive message has been removed from the
FIFO). The PCnet-PCI controller will subsequently up-
date the current RDTE status with the end of frame
(ENP) indication set, write the message byte count
(MCNT) of the complete frame into RMD2 and overwrite
the “current” entries in the CSRs with the “next” entries.
Media Access Control
The Media Access Control engine incorporates the es-
sential protocol requirements for operation of a compli-
ant Ethernet/802.3 node, and provides the interface
between the FIFO sub-system and the Manchester En-
coder/Decoder (MENDEC).
The MAC engine is fully compliant to Section 4 of ISO/
IEC 8802-3 (ANSI/IEEE Standard 1990 Second edition)
and ANSI/IEEE 802.3 (1985).
The MAC engine provides programmable enhanced
features designed to minimize host supervision, bus
utilization, and pre- or post- message processing.
These include the ability to disable retries after a colli-
sion, dynamic FCS generation on a frame-by-frame ba-
sis, and automatic pad field insertion and deletion to
enforce minimum frame size attributes, automatic
retransmission without reloading the FIFO, automatic
deletion of collision fragments, and reduces bus
bandwidth use.
The two primary attributes of the MAC engine are:
Transmit and receive message data encapsulation.
— Framing (frame boundary delimitation, frame
synchronization).
— Addressing (source and destination address
handling).
— Error detection (physical medium transmission
errors).
Media access management.
— Medium allocation (collision avoidance).
— Contention resolution (collision handling).
Transmit and Receive Message Data
Encapsulation
The MAC engine provides minimum frame size enforce-
ment for transmit and receive frames. When
APAD_XMT = 1 (CSR, bit 11), transmit messages will
be padded with sufficient bytes (containing 00h) to en-
sure that the receiving station will observe an informa-
tion field (destination address, source address,
length/type, data and FCS) of 64-bytes. When
ASTRP_RCV = 1 (CSR4, bit 10), the receiver will
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM79C971VCW | PCnet⑩-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus |
| AM79C971 | PCnet⑩-FAST Single-Chip Full-Duplex 10/100 Mbps Ethernet Controller for PCI Local Bus |
| AM79C971KCW | IC LOGIC 16211 24-BIT FET BUS SWITCH -40+85C TSSOP-56 35/TUBE |
| AM79C972BKCW | PCnet⑩-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support |
| AM79C972BKIW | PCnet⑩-FAST+ Enhanced 10/100 Mbps PCI Ethernet Controller with OnNow Support |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C970A | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
| AM79C970AKC | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
| AM79C970AKC\\W | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Advanced Micro Devices 功能描述: |
| AM79C970AKC\W | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。