參數(shù)資料
型號(hào)： AM79C970
廠商： Advanced Micro Devices, Inc.
英文描述： PCnetTM-PCI Single-Chip Ethernet Controller for PCI Local Bus
中文描述： PCnetTM - PCI單芯片以太網(wǎng)控制器的PCI總線
文件頁(yè)數(shù)： 105/168頁(yè)
文件大小： 943K
代理商： AM79C970
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AMD
P R E L I M I N A R Y
1-972
Am79C970
Combinations of watermark set-
tings and LINBC (BCR18, bits
2–0) settings must obey the
following relationship:
watermark (in bytes)
≥
LINBC (in bytes)
Combinations of watermark and
LINBC settings that violate this
rule may cause unexpected
behavior.
DMA Transfer Counter. This
counter contains the maximum
allowable number of transfers to
system memory that the Bus In-
terface Unit will perform during a
single bus mastership period.
The DMA Transfer Counter is not
used to limit the number of trans-
fers during Descriptor transfers.
A value of ZERO will be inter-
preted as one transfer. During
H_RESET or S_RESET a value
of 16 is loaded in the DMA Trans-
fer Counter. The value of
DMATC is unaffected by the as-
sertion of the STOP bit. If the
DMAPLUS bit in CSR4 is set the
DMA Transfer Counter is dis-
abled.
When the DMA Transfer Counter
times out in the middle of a linear
burst, the linear burst will con-
tinue until a legal starting ad-
dress is reached, and then the
PCnet-PCI controller will relin-
quish the bus.
Therefore, if linear bursting is en-
abled, and the user wishes the
PCnet-PCI controller to limit bus
activity to desired_max transfers,
then the DMA Transfer Counter
should be programmed to a value
of:
DMA
Transfer
Counter =
(desired_max DIV
(length of burst in
transfers)) x length
of burst in transfers
7–0 DMATC[7:0]
where DIV is the operation that
yields the INTEGER portion of
the
÷
operation.
Read/write accessible only when
the STOP bit is set.
CSR82: Bus Activity Timer
Bit
Name
Description
31–16
RES
Reserved locations. Written as
ZEROs and read as undefined.
Bus Activity Timer Register. If the
TIMER bit in CSR4 is set, this
register contains the maximum
allowable time that PCnet-PCI
controller will take up on the sys-
tem bus during FIFO data trans-
fers for a single DMA cycle. The
Bus Activity Timer Register does
not limit the number of transfers
during Descriptor transfers.
The DMABAT value is inter-
preted as an unsigned number
with a resolution of 0.1
μ
s. For in-
stance, a value of 51
μ
s would be
programmed with a value of 510.
If the TIMER bit in CSR4 is set,
DMABAT is enabled and must be
initialized by the user. The
DMABAT register is undefined
until written.
If the user has NOT enabled the
Linear Burst function and wishes
the PCnet-PCI controller to limit
bus activity to MAX_TIME micro-
seconds, then the Burst Timer
should be programmed to a value
of:
MAX_TIME– ((11 + 4w) x
(CLK period))
where w = wait states
If the user has enabled the Linear
Burst function and wishes the
PCnet-PCI controller to limit bus
activity to MAX_TIME microsec-
onds, then the Burst Timer
should be programmed to a value
of:
MAX_TIME– (((3+lbs) x w +
10 + lbs) x (CLK period))
where w = wait states and lbs =
linear burst size in number of
transfers per sequence
This is because the PCnet-PCI
controller may use as much as
one linear burst size plus three
transfers in order to complete the
15–0 DMABAT
相關(guān)PDF資料
PDF描述
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AM79C971KCW IC LOGIC 16211 24-BIT FET BUS SWITCH -40+85C TSSOP-56 35/TUBE
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AM79C970A 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
AM79C970AKC 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
AM79C970AKC\\W 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Advanced Micro Devices 功能描述:
AM79C970AKC\W 制造商:Rochester Electronics LLC 功能描述:- Bulk
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