
ASAHI KASEI
[AK4368EG]
MS0529-E-00
2006/07
- 51 -
Register Definitions
Addr Register Name
00H
Power Management
D7
0
RD
0
D6
D5
D4
D3
D2
D1
D0
PMPLL
R/W
0
PMLO
R/W
0
MUTEN
R/W
0
PMHPR
R/W
0
PMHPL
R/W
0
PMDAC
R/W
0
PMVCM
R/W
0
R/W
Default
PMVCM: Power Management for VCOM Block
0: Power OFF (Default)
1: Power ON
PMDAC: Power Management for DAC Blocks
0: Power OFF (Default)
1: Power ON
When the PMDAC bit is changed from “0” to “1”, the DAC is powered-up to the current register values
(ATT value, sampling rate, etc).
PMHPL: Power Management for the left channel of the headphone-amp
0: Power OFF (Default). HPL pin goes to HVSS(0V).
1: Power ON
PMHPR: Power Management for the right channel of the headphone-amp
0: Power OFF (Default). HPR pin goes to HVSS(0V).
1: Power ON
MUTEN: Headphone Amp Mute Control
0: Mute (Default). HPL and HPR pins go to HVSS(0V).
1: Normal operation. HPL and HPR pins go to 0.475 x AVDD.
PMLO: Power Management for Stereo Output
0: Power OFF (Default) LOUT/ROUT pins go to Hi-Z.
1: Power ON
PMPLL: Power Management for PLL
0: Power OFF: EXT mode (Default)
1: Power ON: PLL mode
Each block can be powered-down respectively by writing “0” in each bit of this address. When the PDN pin is “L”,
all blocks are powered-down regardless as setting of this address. In this case, register is initialized to the default
value.
When PMVCM, PMDAC, PMHPL, PMHPR, PMLO, PMPLL and MCKO bits are “0”, all blocks are
powered-down. The register values remain unchanged. Power supply current is 20
μ
A(typ) in this case. For fully
shut down (typ. 1
μ
A), PDN pin should be “L”.
Addr Register Name
D7
D6
01H
PLL Control
FS3
FS2
FS1
R/W
R/W
R/W
R/W
Default
1
0
D5
D4
FS0
R/W
0
D3
PLL3
R/W
0
D2
PLL2
R/W
0
D1
PLL1
R/W
0
D0
PLL0
R/W
0
0
FS3-0: Select Sampling Frequency
PLL mode: Table 2
EXT mode: Table 6
PLL3-0: Select MCKI Frequency
PLL mode: Note 26. Type 1-4 frequency is indicated in Table 2.
Table 1
EXT mode: Disable