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參數(shù)資料
| 型號： | AK4368EG |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | DAC with built-in PLL & HP-AMP |
| 中文描述： | DAC，帶有內(nèi)置的鎖相環(huán) |
| 文件頁數(shù)： | 34/60頁 |
| 文件大?。?/td> | 817K |
| 代理商： | AK4368EG |
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ASAHI KASEI
[AK4368EG]
MS0529-E-00
2006/07
- 34 -
Power-Up/Down Sequence (EXT mode)
1) DAC
→
HP-Amp
Power Supply
(1)
>150ns
PDN pin
PMVCM bit
Clock Input
(3)
SDTI pin
PMDAC bit
DAC Internal
State
PD
Normal Operation
HPL/R pin
PMHPL,
PMHPR bits
(7)
ATTL7-0
ATTR7-0 bits
00H(MUTE)
FFH(0dB)
(9) GD (10) 1061/fs
PD
Normal Operation
00H(MUTE)
FFH(0dB)
(9)
(10)
(7)
(8)
(9) (10)
Don’t care
Don’t care
(8)
(9) (10)
00H(MUTE)
Don’t care
(11)
Don’t care
(2) >0
PD
(6) >2ms(at 3D OFF), >50ms(at 3D ON)
MUTEN bit
DACHL,
DACHR bits
(4) >0
(4) >0
3D1-0 bits
(when 3D is used)
“00”(3D OFF)
“10”(3D ON )
(5) >0
“00”
(6) >2ms, or >50ms
(5) >0
“10”
“00”
Figure 26. Power-up/down sequence of DAC and HP-amp (Don’t care: except Hi-Z)
(1) PDN pin should be set to “H” at least 150ns after power is supplied.
(2) PMVCM and PMDAC bits should be changed to “1” after PDN pin goes “H”.
(3) External clocks (MCKI, BICK, LRCK) are needed to operate the DAC. When the PMDAC bit = “0”, these clocks
can be stopped. The headphone-amp can operate without these clocks.
(4) DACHL and DACHR bits should be changed to “1” after the PMDAC bit is changed to “1”.
(5) When the 3D function is used, 3D1-0 bits should be changed to “10” after DACHL and DACHR bits are changed to
“1”.
(6) When the 3D function is not used, PMHPL, PMHPR and MUTEN bits should be changed to “1” at least 2ms (in case
external capacitance at VCOM pin is 2.2
μ
F) after the DACHL and DACHR bits are changed to “1”. When the 3D
function is used, PMHPL, PMHPR and MUTEN bits should be changed to “1” at least 50ms after 3D1-0 bits are
changed to “10”.
(7) Rise time of the headphone-amp is determined by an external capacitor (C) of the MUTET pin. The rise time up to
VCOM/2 is t
r
= 70k x C(typ). When C=1
μ
F, t
r
= 70ms(typ).
(8) Fall time of the headphone-amp is determined by an external capacitor (C) of the MUTET pin. The fall time down to
VCOM/2 is t
f
= 60k x C(typ). When C=1
μ
F, t
f
= 60ms(typ).
PMHPL and PMHPR bits should be changed to “0” after HPL and HPR pins go to HVSS. After that, the
DACL/DACR bits should be changed to “0” and 3D1-0 bits = “00”.
(9) Analog output corresponding to the digital input has a group delay (GD) of 22/fs(=499
μ
s@fs=44.1kHz).
(10) The ATS bit sets transition time of digital attenuator. Default value is 1061/fs(=24ms@fs=44.1kHz).
(11) The power supply should be switched off after the headphone-amp is powered down (HPL/R pins become “L”).
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