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參數(shù)資料
| 型號(hào)： | AK4368EG |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | DAC with built-in PLL & HP-AMP |
| 中文描述： | DAC，帶有內(nèi)置的鎖相環(huán) |
| 文件頁數(shù)： | 35/60頁 |
| 文件大?。?/td> | 817K |
| 代理商： | AK4368EG |
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ASAHI KASEI
[AK4368EG]
MS0529-E-00
2006/07
- 35 -
2) DAC
→
Lineout
Power Supply
PDN pin
PMVCM bit
Clock Input
(6)
SDTI pin
PMDAC bit
DAC Internal
State
PD(Power-down)
Normal Operation
PMLO bit
ATTL/R7-0 bits
00H(MUTE)
FFH(0dB)
LOUT/ROUT pins
(7)
LMUTE,
ATTS3-0 bits
10H(MUTE)
0FH(0dB)
(8) GD
(9) 1061/fs
(Hi-Z)
PD
Normal Operation
00H(MUTE)
FFH(0dB)
(Hi-Z)
(8)
(9)
(7)
(7)
(8) (9)
Don’t care
Don’t care
Don’t care
(1) >150ns
(2)
>0
(5) >0 (at 3D OFF)
DACL,
DACR bits
(3) >0
3D1-0 bits
(when 3D is used)
(4) >0
“00”(3D OFF)
“01”(3D ON)
“00”
“01”
(5) >0 (at 3D ON)
Figure 27. Power-up/down sequence of DAC and LOUT/ROUT (Don’t care: except Hi-Z)
(1) PDN pin should be set to “H” at least 150ns after power is supplied.
(2) PMVCM bit should be changed to “1” after the PDN pin goes “H”.
(3) DACL and DACR bits should be changed to “1” after the PMVCM bit is changed to “1”.
(4) When the 3D function is used, 3D1-0 bits should be changed to “01” after DACL and DACR bits are changed to “1”.
(5) When the 3D function is not used, the PMDAC and PMLO bits should be changed to “1” after the DACL and DACR
bits are changed to “1”. When the 3D function is used, the PMDAC and PMLO bits should be changed to “1” after
3D1-0 bits are changed to “01”.
(6) External clocks (MCKI, BICK, LRCK) are needed to operate the DAC. When the PMDAC bit = “0”, these clocks
can be stopped. The LOUT/ROUT buffer can operate without these clocks.
(7) When the PMLO bit is changed, pop noise is output from LOUT/ROUT pins.
(8) Analog output corresponding to the digital input has a group delay (GD) of 22fs(=499
μ
s@fs=44.1kHz).
(9) The ATS bit sets the transition time of the digital attenuator. Default value is 1061/fs(=24ms@fs=44.1kHz).
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