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參數(shù)資料
| 型號(hào)： | AK4368EG |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | DAC with built-in PLL & HP-AMP |
| 中文描述： | DAC，帶有內(nèi)置的鎖相環(huán) |
| 文件頁數(shù)： | 17/60頁 |
| 文件大?。?/td> | 817K |
| 代理商： | AK4368EG |
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ASAHI KASEI
[AK4368EG]
MS0529-E-00
2006/07
- 17 -
OPERATION OVERVIEW
System Clock
1) PLL mode (PMPLL bit = “1”)
A fully integrated analog phase locked loop (PLL) generates a clock that is selected by PLL3-0 and FS3-0 bits (refer to
Table 1 and Table 2). MCKO output frequency can be controlled by PS1-0 bits (Table 3). MCKO output can be enabled
by controlling the MCKO bit. The PLL lock time is referred to Table 1. When changing the sampling frequency during
normal operation (PMDAC bit = “1”), the change should occur after the input is muted by SMUTE bit = “1”, or the input
is set to “0” data.
The M/S bit selects either master or slave mode. When the M/S bit = “1” master mode is selected and “0” selects slave
mode. When the AK4368 is in power-down mode (PDN pin = “L”) and then exits the reset state, the AK4368 is in slave
mode. After exiting the reset state, the AK4368 goes to master mode by changing the M/S bit to “1”.
In master mode, when an external clock (11.2896MHz, 12MHz, 13MHz, 14.4MHz, 15.36MHz, 19.2MHz, 19.68MHz,
19.8MHz, 26MHz, 27MHz) is input to MCKI pin, the MCKO, BICK and LRCK clocks are generated by an internal PLL
circuit (Figure 11).
AK4368
DSP or
μ
P
MCKO
BICK
LRCK
SDATA
BCLK
LRCK
SDTO
MCKI
1fs
32fs, 64fs
256fs/128fs/64fs/32fs
27MHz,26MHz,19.8MHz,19.68MHz,
19.2MHz,15.36MHz,14.4MHz,13MHz,
12MHz,11.2896MHz
MCLK
Figure 11. PLL Master Mode
When the AK4368 is used in the master mode, LRCK and BICK pins are in a floating state until the M/S bit becomes “1”.
LRCK and BICK pins of the AK4368 should be pulled-down or pulled-up by a resistor (about 100k
) externally to avoid
the floating state.
In master mode (M/S bits = “1”), LRCK and BICK pins output “L” before the PLL is locked by setting PMPLL =
PMDAC bits = “0”
“1”. At that time, MCKO pin outputs an abnormal frequency clock at MCKO bit = “1”. When
MCKO bit = “0”, MCKO pin outputs “L”. After the PLL is locked, LRCK and BICK start to output the clocks (Table 4).
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