參數(shù)資料
型號: AK4368EG
廠商: Asahi Kasei Microsystems Co.,Ltd
英文描述: DAC with built-in PLL & HP-AMP
中文描述: DAC,帶有內(nèi)置的鎖相環(huán)
文件頁數(shù): 13/60頁
文件大?。?/td> 817K
代理商: AK4368EG
ASAHI KASEI
[AK4368EG]
MS0529-E-00
2006/07
- 13 -
Parameter
Control Interface Timing (I
2
C Bus mode):
(Note 23)
SCL Clock Frequency
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first clock pulse)
Clock Low Time
Clock High Time
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling (Note 24)
SDA Setup Time from SCL Rising
Rise Time of Both SDA and SCL Lines
Fall Time of Both SDA and SCL Lines
Setup Time for Stop Condition
Capacitive Load on Bus
Pulse Width of Spike Noise Suppressed by Input Filter
Power-down & Reset Timing
PDN Pulse Width
(Note 25)
Note 23. I
2
C is a registered trademark of Philips Semiconductors.
Note 24. Data must be held long enough to bridge the 300ns-transition time of SCL.
Note 25. The AK4368 can be reset by bringing PDN pin = “L” to “H” only upon power up.
Symbol
fSCL
tBUF
tHD:STA
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR
tF
tSU:STO
Cb
tSP
tPD
min
-
1.3
0.6
1.3
0.6
0.6
0
0.1
-
-
0.6
-
0
150
typ
-
-
-
-
-
-
-
-
-
-
-
-
-
-
max
400
-
-
-
-
-
-
0.3
0.3
-
400
50
-
Units
kHz
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
pF
ns
ns
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