參數(shù)資料
型號： AK4368EG
廠商： Asahi Kasei Microsystems Co.,Ltd
英文描述： DAC with built-in PLL & HP-AMP
中文描述： DAC，帶有內置的鎖相環(huán)
文件頁數(shù)： 26/60頁
文件大?。?/td> 817K
代理商： AK4368EG
ASAHI KASEI
[AK4368EG]
MS0529-E-00
2006/07
- 26 -
[3] Example of ALC Operation
fs=16kHz
Operation
64ms
+18dB
1 step
1 step
Enable
fs=44.1kHz
Operation
46ms
+18dB
1 step
1 step
Enable
Register Name
Comment
Data
00
C1H
00
0
1
Data
01
C1H
00
0
1
ROTM1-0
REF7-0
LMAT1-0
RATT
ALC
Zero crossing timeout period
Maximum gain at recovery operation
Limiter ATT step
Recovery GAIN step
ALC enable
Table 16. Example of the ALC setting
The following registers should not be changed during the ALC operation. These bits should be changed after the ALC
operation is finished by ALC bit = “0” or PMDAC bits = “0”.
LMAT1-0, ROTM1-0, RATT, REF7-0
ALC = OFF
Note: WR: Write
WR (REF7-0)
WR (LMAT1-0, RATT, ROTM1-0; ALC= “1”)
Example:
Recovery Cycle = 46ms@44.1kHz
Limiter and Recovery Step = 1
Maximum Gain = +18dB
ALC bit = “1”
(1) Addr=0AH, Data=C1H
(2) Addr=0BH, Data=30H
ALC Operation
Figure 19. Registers set-up sequence at ALC operation
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