參數(shù)資料
型號: AK4368EG
廠商: Asahi Kasei Microsystems Co.,Ltd
英文描述: DAC with built-in PLL & HP-AMP
中文描述: DAC,帶有內(nèi)置的鎖相環(huán)
文件頁數(shù): 32/60頁
文件大小: 817K
代理商: AK4368EG
ASAHI KASEI
[AK4368EG]
MS0529-E-00
2006/07
- 32 -
Stereo Line Output (LOUT, ROUT pins)
The common voltage is 0.475 x AVDD. The load resistance is 10k
(min). When the PMLO bit is “1”, the stereo line
output is powered-up. DACL, LINL, MINL, DACR, RINR and MINR bits set the path, respectively. When LOG bit is
“0”(R
1
= 100k) and ATTS3-0 bits is “0FH”(0dB), the gain is 0dB(typ) for all paths. When the LOG bit is “1”(R
1
= 50k),
the DAC path gain is +6dB.
100k(typ)
100k(typ)
+
LOUT/ROUT pin
LIN/RIN pin
MIN pin
R
2
100k(typ)
LINL/RINR bit
MINL/MINR bit
DACL/DACR bit
+
R
2
DACL/DACR
R
1
Figure 24. Summation circuit for stereo line output (LOG bit = “0”)
Analog Output Volume
LOUT/ROUT volume is controlled by ATTS3-0 bits when LMUTE bit = “0” (0dB
30dB, 2dB step, Table 24). Pop
noise occurs when ATTS3-0 bits are changed.
LMUTE
ATTS3-0
0FH
0EH
0DH
0CH
:
:
01H
00H
1
X
Table 24. LOUT/ROUT Volume ATT values (x: Don’t care)
Attenuation
0dB
2dB
4dB
6dB
:
:
28dB
30dB
MUTE
Default
0
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